PFE EMAC0 Invalid Buffer Access Post ECU wakeup

[Avinash_7373]

Hi,

I have configured EMAC0 at 2500 MBPS with required SERDES channel configuration. The Eth communication is up and running during ECU run state. 

After shutting down the applications accessing Eth communication, I trigger the ECU sleep request from ECUM with sets the MCU mode to SOC standby with HSE_CM7 selected as main core. 

Post wakeup the ECU resumes the normal operation, the layers COM, SOAD, TCPIP, ETHIF are working as expected, In the Eth if layer during the API invocation of "Provide TX buffer" returns an error stating TX buffers are not free, followed by no transmission of Eth frames

List of fixes tried resolve the issue:

1. Tried to Shutdown the PFE driver using "Eth_43_Pfe_Deinit" and starting the PFE driver by calling "Eth_43_Pfe_Init" but the CPU gets locked after the execution if Init API.
2. Tried to turndown the Eth controller using Eth_43_Pfe_SetController mode to down and bring it active by setting back the mode to "Active" which led to bus fault

Please let me know the potential fix for this issue. 

P.S>
Configurator Used: EB tresos
Eth PFE RTD version:  1.3.0 
SDK: GOLDVIP

[Joey_z]

Hi,Avinash_7373

Thank you for contacting us.

1.Are the PFEs only used in the M core? Have you used the A core together?

2.Are you using your customer board or our development board?

BR

Joey

[Avinash_7373]

Hi @Joey_z 

1. The PFEs are only being used in M-core
2. I'm using the development board: S32G-VNP-RDB3

Regards,
Avinash V

[Joey_z]

Hi,Avinash_7373

Thank you for your reply.

1.When the SOC entry the mode of standby, about the PFE clock of partition2 will be disabled, you should check if you have reenabled the partition2 after wakeup. You can try to check the  PRTN2_STAT.PCS state before the PFE Init.

2. Check the SERDES if it is a normal function.

BR

Joey

[Avinash_7373]

Hi @Joey_z,

The bitfield in Partition_2 status register remains 1 pre-sleep, it gets updated to 0 during sleep state and it is getting updated back to 1 post wakeup i.e, after the MCU mode is set to normal.

The Serdes is working fine. Additionally I have tried with EMAC2 in RGMII mode where SERDES is not involved in between the ETH Phy connector (RJ45) and the controller (NXPS32G399A) even in this case the issue remained the same.

If there is any restart sequence required for Partition_2 post wakeup, please let me know.

Regards,
Avinash V

[Joey_z]

Hi,Avinash_7373

Your problem is likely to be a PFE initialization issue after wakeup. Check the clock and the related PFE configuration, and ensure that it has been initialized to an ideal state.

1. Check that the PFE initialization is put into bootloader and properly reinitialized in the application after waking up.
2. Check the relevant configurations according to the Standby process. Refer to RM 32.5.5 "Run mode to Standby mode".

BR

Joey

[Joey_z]

Hi,Avinash_7373

Thank you for your reply.

Could you tell me about your operation of standby and wakeup sequence? 

1. How to you set the core and partition?

2.Do you use the bootloader and A core in your application?

BR

Joey

[Avinash_7373]

Hi @Joey_z,

Please find the sleep-wakeup sequence below:

1. I'm requesting ECU sleep mode using API "EcuM_SelectShutdownTarget()"  which in turns sets the MCU mode to standby as per the ECUM implementation.

2. Once the ECUM enters sleep mode it polls for a wakeup event, the CAN transceiver detects the bus activity and set the wakeup event using EcuM_SetWakeupEvent() API then the ECU resumes normal operation.

Regarding bootloader, we have the NXP bootloader (blob is flashed at 0x0) location of flash and the M-core application is flashed at location 0x400000.  A-core is not being used anywhere.

Regards,
Avinash V

[Joey_z · Accepted solution]

Hi，Avinash_7373

Has there been any progress on your issue? If you need continued support, could you please upload your code to the following link so that we can better analyze the problem?

https://support.nxp.com

BR

Joey