Dear Community members,
I am using a reference ARM configuration of ARM Cortex-A53 from an open source OS which is working on i.MX8 and port in on S32G3 RDB3. I am using the u-boot binary & dts files from the yocto build of S32G3 bsp.
The normal port of ARM reference code is working fine, meaning able to boot my RDB3 board, but when it comes to MMU & user process I am facing issues as below:
1. If i try to disable the MMU on RDB3 using the below steps, the execution stops for few sec and then continues. In the imx8 (maaxboard) hardware there is no delay in execution after the mmu disable command.
MRS x3, SCTLR_EL1
BIC x3, x3, (1<<0)
BIC x3, x3, (1<<2)
BIC x3, x3, (1<<12)
MSR SCTLR_EL1, x3
2. When i am updating "ttbr0_el1" with the user level page-table and then try to invalidateLocalTLB using "tlbi vmalle1" the execution stops at "tlbi vmalle1". But the same works fine with i.mx8 (maaxboard)
3. If i update the "ttbr0_el1" and don't invalidateLocalTLB the application code execution continues but later hangs after few update of "ttbr0_el1" in RDB3.
Can you please suggest if there is any additional configuration with respect to aarch64, ARMv8 cortex-a53 for S32g3 than i.mx8 ?
The code snippet for mmu initialization is as below:
/********************************************************************************************************************************/
BEGIN_FUNC(arm_enable_mmu)
/* We call nested functions, follow the ABI. */
stp x29, x30, [sp, #-16]!
mov x29, sp
bl flush_dcache
/* Ensure I-cache, D-cache and mmu are disabled for EL1/Stage1 */
disable_mmu sctlr_el1 , x8
/*
* Invalidate the local I-cache so that any instructions fetched
* speculatively are discarded.
*/
bl invalidate_icache
/*
* DEVICE_nGnRnE 000 00000000
* DEVICE_nGnRE 001 00000100
* DEVICE_GRE 010 00001100
* NORMAL_NC 011 01000100
* NORMAL 100 11111111
* NORMAL_WT 101 10101010
*/
ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
MAIR(0x04, MT_DEVICE_nGnRE) | \
MAIR(0x0c, MT_DEVICE_GRE) | \
MAIR(0x44, MT_NORMAL_NC) | \
MAIR(0xff, MT_NORMAL) | \
MAIR(0xaa, MT_NORMAL_WT)
msr mair_el1, x5
ldr x10, =TCR_TxSZ(48) | TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_TG0_4K | TCR_TG1_4K | TCR_ASID16 | TCR_ISH
mrs x9, ID_AA64MMFR0_EL1
bfi x10, x9, #32, #3
msr tcr_el1, x10
/* Setup page tables */
adrp x8, _boot_pgd_down
msr ttbr0_el1, x8
adrp x8, _boot_pgd_up
msr ttbr1_el1, x8
isb
/* invalidate all TLB entries for EL1 */
tlbi vmalle1is
dsb ish
isb
enable_mmu sctlr_el1 , x8
adrp x8, arm_vector_table
msr vbar_el1, x8
ldp x29, x30, [sp], #16
ret
END_FUNC(arm_enable_mmu)
/********************************************************************************************************************************/
Regards,
Misbah
