Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1

[zyz]

Recently, when using the S32G274 M7 core to read data from flash, I encountered a forced alignment issue. When attempting to read data starting from an address 2n+1, the returned data starts from address 2n. However, reading from address 2n does not have this problem. We are bypassing FEE and directly using the FLS driver to operate the flash. The MCAL version is: SWS32G_RTD_4.4_4.0.2.

Who can help me, thank you.

[carlos_o]

Hi @zyz,

Are you using a custom board? if not is it an RDB or EVB? 

If you are using a custom board, which model of QSPI are you using? 

The problem is when you are doing the bypass of the FEE driver and using directly the FLS? or this is a workaround? 

[zyz]

Hello carlos_o,

Yes, I am using our custom board with QSPI DDR mode. The flash model is MX25UW51245G.

I discovered this issue when directly using FLS.

[carlos_o]

Hi @zyz 

I recommend try first with the IP functions instead of MCAL, you can see how it works at the Spi_Ip_Transfer example. Let me know if the issue persists. 

[zyz · Accepted solution]

Hi carlos_o,
Thank you for your support. I have already solved the problem on my side. This 2-byte alignment issue is caused by the inherent characteristics of FLASH and is not related to the software.

[carlos_o]

Hi @zyz, 

great to hear that. Let us know if there is anything we can do to help.