bug in s32k processor expert flexcan clocks

[momo12]

Hi

I took the example code from flexcan_encrypted_s32k144 and got it running on s32k144 eval board. It works fine. 500 kbaud.

Then I tried to modify the project and chnged the PE clock source from SOSCDIV2 to SYS CLOCK.

Now I get an error in Vector CANOE sayinbg bit error , error position 84.

Any idea why?

[martin_kovar]

Hello,

1. I modified the project and in cancom1:flexcan component changed the PE clock source from SOSCDIV2 to SYS CLOCK. I regenerated all the source files with processor expert and flashed new firmware.
My CAN interface from Vector reports an error: bit error , error position 84.
Why? Processor expert should not provide options which will break CAN communication right?

As it was mentioned above about clock accuracy, I do not recommend you use bus clock for CAN-FD or CAN. The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the CAN bus timing. The crystal oscillator clock has better jitter performance than PLL-generated clocks.

2. I started over again with flexcan_encrypted_s32k144 example project. 500 kbaud, every thign was fine. I modified the project and in cancom1:flexcan component changed the PE clock source from SOSCDIV2 to SYS CLOCK. Additionaly I disabled CAN FD and set the baudrate to 125k in cancom1:flexcan and in sbc_uja11691. I regenerated the files.
Again vector canoe would show error frames only. I managed to get rid of the bug, by manually modifiying bitrate.preDivider from 23 to 22. The value value calculated by processor expert leads errornous frames. It seems that the calculation of .preDivider is wrong here.
Would you please comment on this?

I will ask someone from SDK development team to provide some feedback to this question.

Regards,

Martin

[martin_kovar]

Hello,

here is feedback from SDK development team:

As I mention some times the clock is not exact the value from the pex, in this case can have a little drift.

Another mention is that the algorithm that generate the CBT segments from desired baud rate as input the frequency clock of PE engine is a general one, and some times can’t offer the best match values. Which in this case the user should check the CBT segments values.

Wi will add a disclaimer related to the calculator in the documentation\release note.

Regards,

Martin

[momo12]

Hi

b55689‌

Nana‌

apparently this potential  bug is related to some thing else. when I uncheck "fast IRC regulator" in processore expert the automatically generated bit timings of flexcan work fine , and I get the right frequencies.

what is the "fast IRC regulator enable" bit good for? What does it do?

Why does it solve my issue?

Br

[alexandrunan]

Can you provide exact values for Sys Clock and baud rate for CAN from your use case that not worked ?

I have tested with other baud like 250K and 100K with sys clock at 48Mhz and worked ok, in same cases the frame was wrong decoded but the SYS clock is not precise like OSC Clock and can introduce some drifts. I not used CANoe, I have used another Logic Analyzer to scope and decode signal. 

[momo12]

baudrate is 500k, sys clk , module clk and PE clock are all 48 MHz,

[alexandrunan]

I have tested and worked ok with the parameters from your case, as I added at some frames is failing to decode correctly ! 

And Decoded Frame !

As I sad the drift freq is about 10% calculated in bit-time. The Sys Clock is derived from FIRC clock.

[momo12]

which version of EAR SDK are you using?

The second screen shot: what is the name of the program?

So basically you are sayinf when using can and internal clock, there will be 10% drift?

Is this a constant drift? Any way to compensate that?

[alexandrunan]

I have used S32 SDK S32K14x BETA 1.9.0.

The program is DigiView, and is a Logic Analyzer(HW component). 

To compensate you need to check if cbt segments are the best combination. You can set the time segments by hand for best matching by uncheck the option from PEX "Bitrate to time segments".

[alexandrunan]

Hello, did you regenerate the new cbt segments from driver configuration with the new clock value ?!

Did you used pex for this or only in the register you modified the clock for PE ?

[momo12]

Hi

i just switched SOSCDIV2 to SYS CLOCK in the component view of processor expert, regenerated all the files and compiled it. So I didnt change the code by hand myself.

Isnt this a bug in processor expert and the can library? Processor expert provides choices which will not work.

Could some one from nxp comment on this?

[momo12]

Hi

AnaAldescu‌ and @Petr Stancik can you comment on this?

thx