MPC5777C External RAM read/write speed

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MPC5777C External RAM read/write speed

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Contributor II

Hello

I have two question about MPC5777C platform.

Q1How to improve external SRAM read/write speed

We extended a piece of SRAM(CY7C1480BV33-167AXI) into our design. The r/w speed is not fast as expected. Did i miss some configurations?

Time cost :1320us, 10KB data copy (byte rw).from external sRAM to external sRAM

The project configuration shows blow.

(1) Enable MMU, Enable DCache and ICache

(2) EBI:66Mhz CLK\32bit mode

1620773328_0-1599530396547.png

(2) MMU:Enable Cache for external RAM and internal RAM

微信截图_20200906115342.png

Q2: Is there any example test to determine if the CPU running at highest speed?

We want to know CPU capacity.

 Regards,

Jinus

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NXP TechSupport
NXP TechSupport

Hi, The configuration seems to be correct. You should test performance ideally with 64-bit aligned burst accesses.

You can measure CLKOUT frequency by scope as easiest scope.

Otherwise I can offer clock configurator:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Excel-MPC5777C-clock-configurator/ta-p/1112260

 

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NXP TechSupport
NXP TechSupport

Hi, The configuration seems to be correct. You should test performance ideally with 64-bit aligned burst accesses.

You can measure CLKOUT frequency by scope as easiest scope.

Otherwise I can offer clock configurator:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Excel-MPC5777C-clock-configurator/ta-p/1112260

 

View solution in original post

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Contributor II

Hi,

Thanks very much!

Yes, the CLKOUT configuration was incorrect. The rw speed has great improved after set sram clock to 66Mhz.

I have a new question about cache. Whether writing external or internal RAM, The writing costs should be identical if cache was enabled and has enough memory to hold the data. My test result shows blow.

Why these two platforms behave differently?微信截图_20200911103131.png

 

Regards,

Jinus

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NXP TechSupport
NXP TechSupport

If cache access is configured as write-through (it is being chosen firstly in the MMU TLB and secondly in the cache configuration itself) then write goes directly to the target memory. By default and typically write-through mode is used because it removes potential coherency issues.

If you want basically test only cache write access time, choose copy-back mode.

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