I'm using the NXP Power Estimation Tool (PET).
For STOP1 and STOP2 power savings modes, the max power draw is listed as 8 mA and 9.2 mA respectively. It seems a bit unexpected that the power draw in VLPR and VLPS is listed as 1.57 mA and 37 µA, respectively.
I would think that the power estimation for the STOP modes should be less than that of VLPR and VLPS modes, especially given that STOP modes specify little to no peripherals to be active.
Can anyone shed some light on this for me?
Solved! Go to Solution.
you can take a look at the AN5425, the chapter 3.Power modes description
https://www.nxp.com/search?keyword=an5425&start=0
VLPS:Places the chip in a static state with Low Voltage Detect (LVD) operation off. This is the lowest-power mode in which pin interrupts are functional.
STOP:Places the chip in static state. LVD protection is maintained.
you can take a look at the AN5425, the chapter 3.Power modes description
https://www.nxp.com/search?keyword=an5425&start=0
VLPS:Places the chip in a static state with Low Voltage Detect (LVD) operation off. This is the lowest-power mode in which pin interrupts are functional.
STOP:Places the chip in static state. LVD protection is maintained.