Problem using flexcan_mpc5748g exemple with SDK 3.0.2

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Problem using flexcan_mpc5748g exemple with SDK 3.0.2

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barthod
Contributor I

Hello,

I am currently working on the MPC5748G for my internship. I decided to try the highest SDK version (3.0.2) on this microcontroller.

I ran the flexcan_mpc5748g exemple proposed from S32DS Power.2.1. I followed the "How to run" section (from S32SDK user manual) to set-up the project and build it (with Processor expert).

Flash and debug is performed thanks to the iSystem IC5000 probe.

While debugging the program, everything works perfectly until initialising the flexcan driver. The program is stuck during the FLEXCAN_Enable function (Line 438 of flexcan_hardware_access.c) and more precisely on the while loop (Line 448 flexcan_hardware_access.c) waiting the flexcan to be enabled.

I have this problem on other programs using SDK 3.0.2 but everything works fine with SDK 0.8.1 while initialising the flexcan device.

Do you have any clue or tricks that could help me bypass this issue ?

Thank you in advance for any given answer.

Kind regards,

Xavier

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barthod
Contributor I

Hi,

I changed the clock source to FXOSC and now the module CAN0 is not stuck in FLEXCAN_Enable function, so it has solved my problem and helped me continue my project. The others module (1 to 7) are also working with FS80 source clock. But still I can't figure out why it isn't working with FS80 and SDK 3.0.2 for CAN0.

Is there a register indicating whether or not PE clock is enabled ? I only see AC9_SC[SELCTL] and AC9_SS[SELSTAT] telling me that FS80 is selected (equal to 0).

Kind regards,

 

Xavier

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

PE clock can be sourced either from FXOSC or F40.

MC_ME_GS[S_FXOSC] = 1 shows FXOSC is stable.

BR, Petr

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barthod
Contributor I

Hi,

Sorry I got the CHI and PE clock mixed up.

On my side, MC_ME_GS[S_FXOSC] is equal to 1, before and during the FLEXCAN_DRV_Init function.

If I select F40 or FXOSC for PE clock, the result is the same : CAN_MCR[NOTRDY] is equal to 1.

Oh, one thing I have just noticed is that CAN_MCR[FRZ] and CAN_MCR[HALT] are not unset. I think my debugger is causing trouble* because when I run FLEXCAN_Enable() step y step, CAN_MCR[NOTRDY] is unset by the module. -.-

I think I solved my issue.

Kind regards,

 

Xavier

(*) It wouldn't be the first time...

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

FLEXCAN_Enable function is used to leave Freeze mode to Normal mode. There should be no issue here, unless protocol clock is not active, i think.

BR, Petr

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