HOW to partition S32K116 RAM

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HOW to partition S32K116 RAM

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Contributor IV

Hello :

     Now, I  meet a question .l want to partion S32K116 chip RAM address to several ereas to storage variable.the question is : In debug mode, l  initialize RAM1  area  variable ,the project run sucess.In not debug mode, I initialize RAM1 area variable ,when the project run to set RAM1 area variable (  RAM1_TEST1=1;), the chip will reset. just as bellow :

pastedImage_308.png

     l think the question is l have setted "S32K1xx_flash.ld" file wrong.please tell how to set "S32K1xx_flash.ld".

the memory setting as follow.

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in project ,I add define as bellow

#define SRAM1_STRORG __attribute__ ((section(".SRAM1"))) /* 8k */

#define SRAM1_STRORG_UINT8 SRAM1_STRORG uint8_t
#define SRAM1_STRORGL_UINT16 SRAM1_STRORG uint16_t
#define SRAM1_STRORGL_INT16 SRAM1_STRORG int16_t
#define SRAM1_STRORG_UINT32 SRAM1_STRORG uint32_t

l have upload the project ,please reselve my questing,thank you.

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NXP Employee
NXP Employee

Hi, 

the linker file used in project is missing - it looks that it is linked from your hard drive. 

Jiri

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Contributor IV

Hi

     In project,link file is exist,please check the project again,thank you

pastedImage_1.png

/*
** ###################################################################
** Processor: S32K116 with 17 KB SRAM
** Compiler: GNU C Compiler
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
** Copyright 2017-2018 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/

/* Entry Point */
ENTRY(Reset_Handler)

HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200;

/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from Flash will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0;

/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000000C0
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0


app_programe_dat (RW) : ORIGIN = 0x10000000, LENGTH = 0x00000800 /*2k*/
eeprom_dat (RW) : ORIGIN = 0x10002000, LENGTH = 0x00000800 /*2K*/


/* SRAM_L */
m_custom (RW) : ORIGIN = 0x1FFFFC00, LENGTH = 0x00001400

m_data_RAM1 (RW) : ORIGIN = 0x20001000, LENGTH = 0x00001000
/* SRAM_U */
m_data (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000
m_data_2 (RW) : ORIGIN = 0x20003000, LENGTH = 0x00000800
}

/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
__interrupts_end__ = .;
. = ALIGN(4);
} > m_interrupts

.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config

/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.init) /* section used in crti.o files */
*(.fini) /* section used in crti.o files */
*(.eh_frame) /* section used in crtbegin.o files */
. = ALIGN(4);
} > m_text


.app_programe_data :
{
. = ALIGN(4);
KEEP (*(.app_programe_data))
. = ALIGN(4);
} > app_programe_dat


/* EEPROM */
.eeprom_data :
{
. = ALIGN(4);
KEEP (*(.eeprom_data))
. = ALIGN(4);
} > eeprom_dat


/* Section used by the libgcc.a library for fvp4 */
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text

__etext = .; /* Define a global symbol at end of code. */
__DATA_ROM = .; /* Symbol is used by startup for data initialization. */

.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__RAM_START = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start. */
*(.m_interrupts_ram) /* This is a user defined section. */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end. */
} > m_data

__VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
__RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;

.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* Create a global symbol at data start. */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
__data_end__ = .; /* Define a global symbol at data end. */
} > m_data

__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
__CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */

.code : AT(__CODE_ROM)
{
. = ALIGN(4);
__CODE_RAM = .;
__code_start__ = .; /* Create a global symbol at code start. */
__code_ram_start__ = .;
*(.code_ram) /* Custom section for storing code in RAM */
. = ALIGN(4);
__code_end__ = .; /* Define a global symbol at code end. */
__code_ram_end__ = .;
} > m_data

__CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
__CUSTOM_ROM = __CODE_END;

/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
/* Use this section only when MTB (Micro Trace Buffer) is not used, because MTB uses the same RAM area, as described in S32K Reference Manual. */
.customSectionBlock ORIGIN(m_custom) : AT(__CUSTOM_ROM)
{
__customSectionStart = .;
__customSection_start__ = .;
KEEP(*(.customSection)) /* Keep section even if not referenced. */
__customSection_end__ = .;
} > m_custom
__CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
__SRAM1_ROM = __CUSTOM_END;


/*
.SRAM1 ORIGIN(m_data_RAM1) :AT(__SRAM1_ROM)
{
__SRAM1Start = .;
__SRAM1_start__ = .;
KEEP(*(.SRAM1))
__SRAM1_end__ = .;
} > m_data_RAM1

__SRAM1_END = __SRAM1_ROM + (__SRAM1_end__ - __SRAM1_start__);
*/

.SRAM1 ORIGIN(m_data_RAM1) :
{
. = ALIGN(4);
KEEP(*(.SRAM1))
. = ALIGN(4);
} > m_data_RAM1


/* Uninitialized data section. */
.bss :
{
/* This is used by the startup in order to initialize the .bss section. */
. = ALIGN(4);
__BSS_START = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__BSS_END = .;
} > m_data_2

/* Put heap section after the program data */
.heap :
{
. = ALIGN(8);
__end__ = .;
__heap_start__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
PROVIDE(__end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .;
__heap_end__ = .;
} > m_data_2

/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
__RAM_END = __StackTop;

.stack __StackLimit :
{
. = ALIGN(8);
__stack_start__ = .;
. += STACK_SIZE;
__stack_end__ = .;
} > m_data_2

.ARM.attributes 0 : { *(.ARM.attributes) }

ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

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NXP Employee
NXP Employee

Hi, 

there is some issue with OpenSDA PE Micro. I can successfully attach with Segger J-Link and Lauterbach. I added blinking  LED  when program is running and it starts normally blinking after board reset. 

Thanks for reporting this issue. I'll log as a bug. The workaround is use another non PE Micro debug probe. 

Jiri 

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Contributor IV

Hi 

     First ,my question is :in debug mode,use the project l upload is narmal,when l use pemcrio dowmload the .elf file to s32k116 chip, the s32k116 chip will reset always.

     Second, how to partion the S32K116 RAM, can you give me a suggest or example project. my development environment is S32DS software.Can you help me ? thank you.....

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NXP Employee
NXP Employee

Hi, 

Actually on my side is project working even if  .elf file is uploaded by PE Micro (the LED is blinking after reset). But PE Micro is not able attach into running board. I already reported it as a bug. 

I'm not sure what you mean by RAM partitioning. If you mean add custom section into linker file - you are doing it right. 

Jiri 

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Contributor IV

Hi

    thank you for you response.

    the reason why l need to partion RAM to several area is that l want copy DFLASH store data to RAM after system  power on. During system power up,l will change RAM area variable data.Before power down, l will copy data from  RAM to Dflash. the variable is too much ,so l can not copy data one by one, l need oprate it batch.

pastedImage_1.png

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NXP Employee
NXP Employee

Hi, 

the best option is using Emulated EEPROM - if your data can fit into 2kB size. Here is simple example - https://community.nxp.com/docs/DOC-340114 and store your data into structure for example. 

Otherwise you need to crate some memory management by yourself - something like "save" function where you can specify RAM start address  and RAM end address and store this area into dflash.

Jiri

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Contributor IV

Hi ,

     l need two RAM area, each area need 2kB size,l am so tangle for this problem.

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NXP Employee
NXP Employee

Hi, 

I can reproduce the issue, but didn't find solution yet. Even with disabled optimizations - wihthout debugger MCU ends in reset loop. 

Jiri 

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