spi data transmission

[lssuer]

when i transmit an array of data through the spi the value of the first entry of the array shows up on the receiver for all the array entries. When i use break points the data is transmitted fine, and does what i mentioned earlier when the code is ran at speed. Ive tried delays but it doesnt work. Does anyone know if i have to clear the data register before i use it each time or if there is a trick that i am missing like reading from the register twice. Thanks

[bigmac]

Hello Issuer,

Is your "receiver" the master or slave device?

Regards,
Mac

[lssuer]

heres my reciever code and my reciever is the slave, also i am using the MC9S12DP256 micro. thanks for any help you can provide.
Code:

for (i = 0; i5; i++){PTM |= 0x40;while(!(SPI0SR & 0x80));switch(i){case 0:port_enable = SPI0DR;port_enable = SPI0DR;break;case 1:display_port = SPI0DR;display_port = SPI0DR;break;case 2:sample_rate = SPI0DR;sample_rate = SPI0DR;break;case 3:module_number = SPI0DR;module_number = SPI0DR;break;case 4:last_flg = SPI0DR;last_flg = SPI0DR;break;default:temp = SPI0DR;temp = SPI0DR;}for (l=0; l200000; l++){PTM &= 0xBF;}}

 
(Alban changed code format using "SRC" button)

Message Edited by Alban on 05-09-2006 10:56 AM

[bigmac]

Hello Issuer,

For the slave device, the /SS input will need to be driven from the master, or alternatively might be tied permanently active low.

However, if the latter case is used, the setting CPHA = 1 is required (it will not work for CPHA = 0). The settings for both CPHA and CPOL must be identical for master and slave.

Your Port M output would seem unnecessary for the slave end.  At the master end, if the /SS pin is configured as  /SS input, this should be tied to Vdd.  However, if configured as a /SS output, it could be connected to /SS input at the slave.

Regards,
Mac

[rhinoceroshead]

What you have here looks fine to me, except the for loops - which I assume got formatted incorrectly by the forum.  You shouldn't need to read SPI0DR twice, but that shouldn't hurt anything either.  I'm also curious about the way you're manipulating port M6.  Is this connected to SS on the transmitter?

It would be interesting to see the way your SPI is configured on both the transmitter and receiver.  Do you have the mode fault detection enabled?

[rhinoceroshead]

It sounds to me like your receiver is not waiting for the new byte to show up before writing it to the array.  Are you polling the SPIF bit to see when there is a new byte received?  Or are you using an interrupt?

Can you post your receiver's code?

To answer your question,  no, you should not have to clear the data register.

Which chip are you using?

Message Edited by rhinoceroshead on 05-07-200611:04 PM

[peg]

Hi issuer,

The first thing I would do is send a smaller array.
If the receivers array is still FULL of the first byte, then you have probably got something like what rhino is describing. At least this should start you down the path to locating the problem.

There has been many threads on this topic recently. Probably a good idea to search them out (8 and 16 bit forums)

Regards Peg