read BKGD signal

[100asong]

Hi,Sir.

     The following function want to read byte from target in BKGD line.

But I find that the signal waveform is wrong from target.Please see it in the attachment.

Please give me support about it.

void bdmInByte()
{
  asm{
    sei
    ldab #8
    ldx #0
  Next_In:
    bset BKGD_Direction,1 
    lslx
    bclr BKGD_Name,1 //pull-down the BKGD pin ,4 target clock

    bset BKGD_Name,1 //4 cycle,out1         ,   4 target clock

    bclr BKGD_Direction,1//to input ,4 cycles  , 4 target clock
   
    ldaa BKGD_Name                            

    beq In0
    incx
  In0:
    decb
    bne Next_In
    bclr BKGD_Direction,1
     tfr x,a
    staa g_InData;
    cli     
  }

}

[kef]

You have to not drive target BDM pin high. You should use on of these options:

1) use open collector/open drain buffer between host and target MCUs

2) use pin with wired or capability

3) Use software wired or mode. You can latch "0" to port output latch while direction bit is "0". Then you can set or clear direction bit to get driven low or not driven low on output pin.

Since timing is tight, calculating bus cycles you should take into account when actually write happens, on which 1 out of 4 bset/bclr bus clocks. Bset/bclr reads port in the first bus cycle and writes back to the port on 3rd bus cycle.

[100asong]

You have to not drive target BDM pin high. You should use on of these options:

1) use open collector/open drain buffer between host and target MCUs

2) use pin with wired or capability

3) Use software wired or mode. You can latch "0" to port output latch while direction bit is "0". Then you can set or clear direction bit to get driven low or not driven low on output pin.

Since timing is tight, calculating bus cycles you should take into account when actually write happens, on which 1 out of 4 bset/bclr bus clocks. Bset/bclr reads port in the first bus cycle and writes back to the port on 3rd bus cycle.

Dear Sir.Thans for your help.

I don't know whether my comprehension is right here.

for 1):

 host cpu is MC9S12xep100,PB0  links BKGD of target MCU(another MC9s12xep100).So I think it is open drain.

I have difficulty in 2) and 3).

Could you please give me the detailed code about 3).

Thank a lot.

[kef]

No, PB0 is push-pull. Open drain can be ports which have corresponding WOMx register. I found 3 WOMx in S12XE datasheet. WOMS, WOMM, WOML. When you set WOMx bit, corresponding pin is configured in open drain (wired OR) mode. For example after setting WOMM0 bit and DDRM0 bits, setting PTM0=0 will drive PTM0 pin low, but setting PTM0=1 will not drive PTM0 pin in any direction.

Emulating open drain mode for PB0 can be done this way:

1)initially PB0 direction is input

    DDRB &= ~(1<<0);

2) you latch zero to PB0 output latch

   PORTB &= ~(1<<0);

3) with zero latched to PORTB, to drive PB0 low you set DDRB0 bit

   DDRB |= (1<<0);

to stop driving PB0 you clear DDRB0 bit

   DDRB &= ~(1<<0);

Warning! If XGATE is writing to PORTB, or if interrupts are enabled and some ISR write to PORTB, then special care should be taken, else background task can make PB0 driven high. This will happen if ISR occurs when DDRB0==0. Bsetting or bclearing PORTB with (1<<n) will latch to PB0 value read from PB0, and value read can be "1". For example if some background task uses PB7 pin, then

    PORTA_BIT7 = 0;  // wrong

    PORTA_BIT7 = 1;  // wrong

    PORTA_BIT7 |= (1<<7);  // wrong

    PORTA_BIT7 &= ~(1<<7);  // wrong

Safe way to clear PB7 from background, keeping zero latched in PB0 is this:

   PORTB = (PORTB & ~(1<<7)) & ~(1<<0);

,or to set PB7

   PORTB = (PORTB | (1<<7)) & ~(1<<0);

[100asong]

Hi,Dear sir

       So happy to get your message,Sorry for replying so later.

        Thanks for your helps.

        

Best Regards,