Hi Congmin,
I suppose, that your question is connected to the previous thread:
https://community.nxp.com/thread/451254
Correct?
We should toggle with SBK bit for transmitting break signal. For example:
SCI0CR2_SBK = 1; //START TO SEND
SCI0CR2_SBK = 0; //STOP SENDING BREAK
A break character contains all logic 0s and has no start, stop, or parity bit. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame.
So, when we just set SBK bit without clearing SBK bit (as in the code in next thread), the SCI TX output will be kept in dominant level whole time. However, the LIN PHY has TxD-dominant timeout feature enabled by default. Therefore, the LIN transmitter will be shut down after a while and you will not see the dominant level at LIN pin.
Please check LPSR_LPDT flag.
There is the LIN stack:
http://www.nxp.com/assets/downloads/data/en/device-drivers/FSL_LIN_2.X_STACK.zip
The simple LIN example code for your inspiration (for the older S12G family) may be found here:
https://community.nxp.com/docs/DOC-93792
Other obvious and potential issues in your code:
- please be careful with read-modify-write commands like CPMUCOP_CR2 = 1;. Some of registers/bits can be written just once in normal mode (like the content of CPMUCOP register). So, the next commands will be ignored. I would like to recommend commands like CPUMCOP=0x04; for such registers. The CPUMCOP and MODRRx registers are the typical examples.
- You enabled COP watchdog. However, I do not see any for feeding it (write into CPMUARMCOP register).
- Commands
SCI0SR2_AMAP = 0;//
SCI0ACR2_IREN = 0;//红外遥控解码 功能禁止
doesn’t make sense, since SCI0ACR2_IREN bit is available only when you switch into the alternative map (AMAP=1).
- When you disable external oscillator (OSCE = 0), you cannot disable PLL. The PLL may be disabled only when clock from the external oscillator is enabled and validated (UPOSC=1). I would like to recommend from this reason also configure SYNR, REFDV, POSTDIV registers by single write – less confusion for PLL circuit.
I hope it helps you.
Have a great day,
Radek
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