Hi,
the COP vector is still on the same place so app+bootloader has no influence on performance.
The issue sounds me like code of your uses two different ways where one enables COP and the other does not.
I would suggest you, in the first step, to signalize somehow the COP is enabled.
Each bit in the set of register bytes has defined reset status. So, after each type of reset the COP is disabled (COPCTL) except there is initial value (which automatically starts COP) stored in the flash FOPT register at the address 0xFFFF0E which is automatically copied to COPCTL during reset.
The CPMURFLG is has no reset value defined by source of the reset.
The data sheet states:
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. COPRF is set to 1 when COP reset occurs. Unaffected by System Reset. Cleared by power on reset.
4. OMRF is set to 1 when an oscillator clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset.
5. PMRF is set to 1 when a PLL clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset.
System reset = each possible reset source except power on.
As you can see you are responsible to clear the flag if you do not want to cause incorrect recognition after the new system reset.
Be sure you are clearing and correctly clear the flags after reset source tests. For more information please read Clearing and Disabling Interrupt Flags.pdf:
http://www.freescale.com/files/microcontrollers/doc/app_note/AN2554.pdf
The reset sequence is described in the data sheet:
8.5.2 Description of Reset Operation
Figure 8-40. RESET Timing
Best regards,
Ladislav
