Simultaneous events on the S12

[Bee]

I've been using the S12 and the UF32 for a few years. A problem that seems to come up has me confused. I have to entertain multiple Input Capture events on both cpu's. It's easy to set up ISR's and set the TIE and other registers to capture the events. Now the most critical event set up is when 2 or more events happen simultaneously. I do this test by using the same 1 KHz (square wave) input to 2 IC pins. In both CPU's, only one ISR fires. On the UF32, the flag is set for the second event, but the ISR is never invoked. In that case, I learned to handle the 'other' flag in the current ISR and process the event. On the S12 (MC9S12DJ256B..-80pin), the 'other' event's flag is Not even set. So although I can handle its event, I don't know to do it. Ignoring it makes chaos. The fix is to make the second event happen on the falling edge. That works for event processing (proving my setup is correct), but not for reality of events.

Has anyone else experienced this kind of behavior. I'm ready to turn in a Service Request to see if FSL has any help.

Thanks.

[kef]

It looks like you are improperly clearing timer flags. Simultaneous timer capture or output compare events pose no problems for ECT and TIM timers. You should know that timer and not only timer but many other interrupt flags can't be cleared involving bset and sometimes bclr intructions. If you are using C and not assembler then you also should know how to do it properly from C:

1) Don't use bitfields when clearing flags. For example TFLG1_C1F=1; is wrong. It clears not only TC1 flag but also flags that were set before this C line.

TFLG_C1F=0; // <- this is also bad, It won't clear TC1 flag but will clear all other flags that are set.

2) TFLG1 |= 1; // this is wrong. This is same to TFLG1_C1F=1;

3) TFLG1 &= 1; // this is OK

4) TFLG1 = 1;  // this is OK

Regards

[Bee]

Thanks, kef. How stupid of me! And I should know better. Turns out that I was cleaning up the code in a 'broom-sweep' method (optimize, etc) and forgot all about NOT using the BSET to clear a flag. It used to be BLCR with the complement of the flag. So I fell into the unusual trap and because the interrupts did not happen simultaneously until I turn on my severe testing mode, I never saw the effects of my cleaning up.

I glad there's someone to help me out..