(Simple) Timer Problem on MC9S12A32

[drewrainwater]

I'm trying to port old HC11 code (written by another employee) to the MC9S12A32, and this is my first attempt at working with the Motorola/Freescale family of MCUs.

The problem I'm seeing is that the C0F flag is immediately set when I initialize the timer (by enabling the Output Compare on Channel 0 and enabling the timer by setting TEN) :

---

 TIMERINIT   LDAA #$01
            STAA TIOS     ;SET CHANNEL 0 TO OUTPUT COMPARE
           
            LDAA #$80
            STAA TSCR1    ;ENABLE TIMER
          
            RTS

---

Later, when I'm trying to create a 15ms delay, the C0F flag is already set and my delay subroutine exits too quickly.  I have tried to clear the C0F flag by writing a 1 to the bit (TFLG1.1), but that either fails or the flag is immediately set again before I can read it with the next instruction

---

 DELAY
       LDAA        #$01
       STAA        TFLG1           ;CLEAR OC0F
       LDD         TCNT.H          ;GET PRESENT TIMER VALUE
       ADDD        DLY              ;ADD REQUIRED DELAY
       STD         TC0.H           ;STORE IN COMPARE 0
     
       
LP1           LDAB        TFLG1           ;WAIT FOR COMPARE
       STAB        TFLAG
       BRCLR       TFLAG,  $01,  LP1

       RTS

---

Can anyone offer a suggestion why the C0F flag is being set immediately and/or continuously?

Also, as a side question, in CodeWarrior, there doesn't seem to be an easy way to watch the Timer registers change as I step through instructions (which would make this problem easier to diagnose).  My Memory window doesn't update the contents of memory locations as I step through--should this be the case?

Thanks in advance.

Drew

[kef]

All your code is OK. Is DLY variable set up to the same constant as in HC11 case? Did you take into account that HC11 bus clock is oscilator clock/4, while S12 bus clock is oscilator clock/2 (while PLL clock is not selected).

To ease timer code debugging, you should set TSFRZ bit. By default it is not set, and timer keeps ticking while CPU is stopped on breakpoint or single stepped. With TSFRZ=1, for example TCNT will increment only while CPU is executing some instructions.

Regarding compare flag is set "immediately". It is not immediately. It happens when free running TCNT counter ticks up and matches compare value. With 16MHz oscilator, 8MHz bus clock and 1:1 timer prescaler, 16bit timer overflows every 8.192ms . Of course output compare flag is set to 1 also every 8.192ms.