SPI Slave MC9S12G

[vengeful]

Hello All,

Seem to have run into a bit of a problem here, setting up the above micro for slave operation and when I am ready to send something, I alert the Master and then enable Transmit Interrupts. In the interrupt, I test for empty, and then load up the SPI0DRL register, the Interrupt is then disabled when the data is transmitted out. However, while in debug mode, I see that the SPI0DRL register does not get populated and hence on the Master side I see 00's coming through. The physical connections seem to work, as I watched them on a scope, SS is low, and I get clocked, but this SPI buffer just never gets populated.

Setup:

SPI0BR = 0x01;

//Baud Rate Divisor = 4 -> SPI speed of 4Mbps  ( Baud = Bus Clock/ BR Divisor)

SPI0CR2 = 0;

SPI0CR1 = 0b01000000;    //Rx interrupt disabled, SPI enabled, Tx interrupt disabled, Slave mode, Default clock polarity & phase, Manual Slave Select, MSB first

In main :

Wait for 2 Second timer to expire, then Alert the master of data to send, Enable transmit SPI int

In Interrupt;

     SPI0DRL = Data;  // Somehow this does not seem to get popuplated

Using Codewarrior IDE, MC9S12G192 and Multilink ICD

[kef]

• In the interrupt, I test for empty, and then load up the SPI0DRL register

Do you mean you read SPI status register and then write data register? OK then.

You didn't mention what SPI interrupt you are using, transfer complete interrupt (SPIF + SPIE) or transmit buffer empty interrupt (SPTEF + SPTIE). First one is triggered after master clocks data in/out. On slave you don't need to disable it. Once data is clocked by master and you clear SPIF flag (reading SPI status, and then reading SPI data), SPIF won't set again until next byte from master. So no need to disable interrupt.

SPTEF interrupt is more suitable for what you trying to do. You could enable SPTEF, then since SPTEF is normally set (buffer empty), this interrupt will fire, you could load SPI buffe, exit from interrupt, then signal master you have some data.

Are you receiving any SPI data from master? If so, then you shoud service each SPIF=1 event.

[vengeful]

Sorry about that, yes I am already using Transmit Buffer empty Int except the order that its currently running in is: Drop the line low, to indicate to the master that I have data to send and then enable the transmit empty int. I will try it the other way around. Regardless though, any particular reason as to why I dont see any data being passed to the SPIDRL register?

At this point, I just want to be able to receive from the slave, will try sending from master afterward.