S12ZVL nested interruputs

[fanziyu]

Hello,everyone I have met a prolblem,could you help me?

mcu: S12ZVL64
Problem: 

Low priority:   timer0 interrupt, ADC interrupt, LIN Interrupt
High priority:  timer1 channel 0 capture interrupt

First target : The high priority interrupt can interrupt low executing interrupt; I can make it.

Second target: the low priority interrupt will not interrupt other low executing interrupt. Can this be achieved? I don't understand how to achieve.

I have download AN2617.

Thanks!

[lama · Accepted solution]

If you set priority of interrupts in correct way you do not need to work with stack. You primary question was how to interrupt interrupt with higher priority. This is not a standard process. Usually we use standard way of prioritization given by priority setup. As I wrote, I presented higher level of interupt nesting on the basis of understanding of your question.

Demonstration of interrupt priority setup.
You set it correctly. Only for other guys who will look here.

//******************************************************************************
// see Table 1-12. Interrupt Vector Locations in the data sheet to get vector address
//******************************************************************************
#define TIM0_0 0x1CC // vector address => CFADDR base = (0x1CC/4) & 0x78 = 0x73 & 0x78 = 0X70 ; 0x78 is mask on the used register bits
#define TIM0_1 0x1C8 // vector address => CFADDR base = (0x1C8/4) & 0x78 = 0x72 & 0x78 = 0X70 ; 0x78 is mask on the used register bits
#define TIM0_2 0x1C4 // vector address => CFADDR base = (0x1C4/4) & 0x78 = 0x71 & 0x78 = 0X70 ; 0x78 is mask on the used register bits
#define TIM0_3 0x1C0 // vector address => CFADDR base = (0x1C0/4) & 0x78 = 0x70 & 0x78 = 0X70 ; 0x78 is mask on the used register bits
#define TIM0_4 0x1BC // vector address => CFADDR base = (0x1BC/4) & 0x78 = 0x6F & 0X78 = 0X68 ; 0x78 is mask on the used register bits

#define SET_PRIORITY(vec_adr, priority) \
INT_CFADDR= ((vec_adr) / 4) & 0x78; \ // or INT_CFADDR_INT_CFADDR = 0xD; if we want to write to bits only as you presented in your reply
INT_CFDATA_ARR[(((vec_adr) / 4) & 0x07)]= (priority)

// TEST: TIM0_2 ARRAY INDEX SHOULD BE 1 ... (0x1C4 / 4) & 0x07 = 0x71 & 0x07 = 1
// TEST: TIM0_3 ARRAY INDEX SHOULD BE 0 ... (0x1C0 / 4) & 0x07 = 0x70 & 0x07 = 0
// TEST: TIM0_4 ARRAY INDEX SHOULD BE 7 ... (0x1BC / 4) & 0x07 = 0x6F & 0x07 = 7

Now in the code, whenewer you want yu can change the priority.

#define SET_PRIORITY(TIM_0_4, 5); // set priority 5 for TIM0 channel 4; note the priority wil be valid for next priority comparison of priorities coming into interrupt procesing process

As I wrote before, stack is not necessary to be used if you set correct priorities at the beginning and you do not need to interrupt currently executed interrupt of higher priority than interrupt which is asking for service and has lower priority. If you want to interrupt a currently executed interrupt of lower priority than interrupt which is asking for service then it is enough if you at the beginning of the interrupt clear I bit to make interrupt to be interruptible. In this case nesting work in natural way.

If you have problem to set priorities from application point of view then deep analysis of SW, required interrupts and timing must be done on low level together with measurements of times.

Project stack size is not able to be calculated if you nest interrupts or you use stack as a temporary storage place. In this case it is good to create larger stack and fill it with known value. Then perform test and check how deep stack is. This approach is usually used also to check stack overflows if allocations are nod correctly made or stack is only filled but not released.

... I hope I have not made a mistake. I only directly write it here without testing.
Best regards,
Ladislav

[lama]

Hi,

I have never programmed this for this family and there is no plan to do it in near future. However, I can provide you a suggestion how to do it. I hope I am not wrong. ( I know, stimulating info    )

s12zcpu MANUAL

2.2.5.2 IPL[2:0]
The IPL bits allow the nesting of interrupts, blocking interrupts of a lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to
the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The IPL bits are restored from the exception stack frame by
executing the RTI instruction.

So, if you call function
asm CLI;
at the beginning of any interrupt subroutine then it will be interruptible by interrupt with higher priority level than stored in the IPL register.

Moreover, if you are experienced guy and you know what you are doing then it is possible to rewrite value at the stack with lower priority value and make also served interrupt to be interruptible by interrupt with lower priority.
But this is next level of programming when you have to understand how to get pointer to stack where the priority of the services interrupt is stored, how to rewrite it and if necessary write it back.
I have never made it for this family of the MCU but something similar I made for old S12XD devices family(different familly but also IPL register) See description at the beginning of the code ... starting with "The philosophy of the code is that all timer interrupts have interrupt priority=1." The procedure of the game with CCR and IPL is also noted in the example bellow in the function interrupt 8 void TCO_Isr(void). I have also to mention this is not an assembler of S12Z but S12X devices.
If I were you I would debug each next added program step to see how it works and not. Moreover, I would use new simple project which must be as simple as possible to exclude all unexpected issues.
You can look at the main.c file I attached bellow.
Moreover, a lot of explanation says statement from the reference manual of S12Z. Item 2.b direct you to the solution how to interrupt currently served interrupt with higher priority level then coming interrupt.

The following conditions must be met for an I-bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The setup in the configuration register associated with the interrupt request channel must meet the
following conditions:
a) The priority level must be set to non zero.
b) The priority level must be greater than the current interrupt processing level in the condition
code register (CCW) of the CPU (PRIOLVL[2:0] > IPL[2:0]).
3. The I-bit in the condition code register (CCW) of the CPU must be cleared.
4. There is no access violation interrupt request pending.
5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending.

As you can see if you are able to program in assembler and understand what and how you do with stack and CCR it is possible. Dangerous but possible.

Best regards,

Ladislav

/*==============================================================================
Project Name: main.c
Last modified: Jul/11/2006
By: r62780
******************************************************************************
Description: XDP512 - ECT+NestedISRover7-CW45
Documentation: MC9S12XDP512V2.pdf
This software is classified as Engineering Sample Software.
******************************************************************************
- this sample software was tested on SK-S12XDP512 (EVB)
- the board includes 16MHz crystal / the MCU's bus frequency 8MHz is used
- the mask set number was 0L15Y

- the sample software does:
. solves interrrupt nestin if more than 7 interrupt have to be nested.
. runs 8 function in specific/demanded order and time of the launch.
. timing is made by means of 8 channel of ECT timer
. start of each function is visualized by clearing given pin of the PORTB.
TC0isr->call function0()->clear PORTB.0
TC1isr->call function1()->clear PORTB.1
...
TC7isr->call function7()->clear PORTB.7
. beginning (start) of intervals is visualized by settings PORTB=0xFF.
. interval till functionX is started is claculated as:
interval = TCx * dt = TCx * (prescaler/fbus)
TCx = interval / (prescaller/fbus) = interval * fbus / prescaler [-;us,MHz,-]

Max interval can be calculated as interval[us]=65535*prescaler/fbus[MHz]
and setup precision is dt=prescaler/fbus

for fbus = 8MHz
If prescaler = 1 then max interval is 8.191875 ms; dt = 0.125 us
If prescaler = 2 then max interval is 16.38375 ms; dt = 0.25 us
If prescaler = 4 then max interval is 32.7675 ms; dt = 0.5 us
If prescaler = 8 then max interval is 65.535 ms; dt = 1 us
If prescaler = 16 then max interval is 131.07 ms; dt = 2 us
If prescaler = 32 then max interval is 262.14 ms; dt = 4 us
If prescaler = 64 then max interval is 524.28 ms; dt = 8 us
If prescaler = 128 then max interval is 1048.56 ms; dt = 16 us

Let prescaler = 1 and:
interval0 = 25 us => INTERVAL0 = interval0/dt = 25 /0.125 = 200
interval1 = 50 us => INTERVAL1 = interval0/dt = 50 /0.125 = 400
interval2 = 77 us => INTERVAL2 = interval0/dt = 77 /0.125 = 600
interval3 = 100 us => INTERVAL3 = interval0/dt = 100/0.125 = 800
interval4 = 125 us => INTERVAL4 = interval0/dt = 125/0.125 = 1000
interval5 = 150 us => INTERVAL5 = interval0/dt = 150/0.125 = 1200
interval6 = 175 us => INTERVAL6 = interval0/dt = 175/0.125 = 1400
interval7 = 200 us => INTERVAL7 = interval0/dt = 200/0.125 = 1600

. The philosophy of the code is that all timer interrupts have interrupt priority=1
Only TC0 interrupt has priority 7 - it will start function which shoul start first.
When TCO interrupt is launched the priority structure is changed and the highest priority
gets TC1 interrupt. TC0 interrupt priority is changed to 1. Moreover IPL (running
interrupt priority level) must be changed inside the CCRW (status and control register)
It is made because we want to be TCOisr interruptible by interrupt with higher priority.
This procedure is performed inside each interrupt.
. Each interrupt procedure is set to have loger duration than interval between channel interrupts.
So, TC1 interrupts TC0, TC2 interrupts TC1,...,TC7 interrupts TC6.
As soon as TC7isr is finished TC6isr will continue.
As soon as TC6isr is finished TC5isr will continue.
...
As soon as TC2isr is finished TC1isr will continue.
When all interrupts are finished progaram goes to the beginning of the main loop
and repeats cycle with new values of TC0..TC7 on the base of new value of Timer TCNT.
==============================================================================*/
//==============================================================================
// SETUP DEFINITIONS
//==============================================================================
#define INTERVAL0 200 //25us
#define INTERVAL1 400 //50us
#define INTERVAL2 600
#define INTERVAL3 800
#define INTERVAL4 1000
#define INTERVAL5 1200
#define INTERVAL6 1400
#define INTERVAL7 1600

// COMPENSATIONX represents duration (in TCNT counts = busclock/prescaler) from the moment
// interrupt request to the time of the firs instruction in the funcitionX()
// Note1: INTERVALX must not less value than COMPENSATION
// Note2: values were get by means of debugger and oscilloscope

#define COMPENSATION 65+8 //8 is time to interrupt

#include <hidef.h> /* common defines and macros */
#include <mc9s12xdp512.h> /* derivative information */
#pragma LINK_INFO DERIVATIVE "mc9s12xdp512"
//==============================================================================
#include <string.h>
#include "xgate.h"
//==============================================================================
// COMMON DEFINITIONS
//==============================================================================
#define UBYTE unsigned char
#define SBYTE char
#define UWORD unsigned int
#define SWORD int
#define ULONG unsigned long
#define SLONG long
//==============================================================================
#define ROUTE_INTERRUPT(vec_adr, cfdata) \
INT_CFADDR= (vec_adr) & 0xF0; \
INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)
//==============================================================================
// the same definition used for another purpose so more fitting name
#define SET_CPU_PRIORITY(vec_adr, cfdata) \
INT_CFADDR= (vec_adr) & 0xF0; \
INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)
//==============================================================================
#define ECT_CH7 0xE0 // vector address
#define ECT_CH6 0xE2 // vector address
#define ECT_CH5 0xE4 // vector address
#define ECT_CH4 0xE6 // vector address
#define ECT_CH3 0xE8 // vector address
#define ECT_CH2 0xEA // vector address
#define ECT_CH1 0xEC // vector address
#define ECT_CH0 0xEE // vector address
//==============================================================================
// FUNCTION PROTOTYPES
//==============================================================================
void ECT_Init(void);
void function0(void);
void function1(void);
void function2(void);
void function3(void);
void function4(void);
void function5(void);
void function6(void);
void function7(void);
static void SetupXGATE(void);
//==============================================================================
// Variables section
//==============================================================================
UWORD baseTime;
UBYTE again=0;
volatile UWORD i0,i1,i2,i3,i4,i5,i6,i7;
//==============================================================================
// CODE section
//==============================================================================
static void SetupXGATE(void)
{
// initialize the XGATE vector block and set the XGVBR register to its start address
XGVBR= (unsigned int)(void*__far)(XGATE_VectorTable - XGATE_VECTOR_OFFSET);
ROUTE_INTERRUPT(ECT_CH7, 0x01); // switch ECT_CH7 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH6, 0x01); // switch ECT_CH6 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH5, 0x01); // switch ECT_CH5 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH4, 0x01); // switch ECT_CH4 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH3, 0x01); // switch ECT_CH3 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH2, 0x01); // switch ECT_CH2 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH1, 0x01); // switch ECT_CH1 interrupt to CPU ; RQST=0 and PRIO=1
ROUTE_INTERRUPT(ECT_CH0, 0x07); // switch ECT_CH0 interrupt to CPU ; RQST=0 and PRIO=7
// enable XGATE mode and interrupts
XGMCTL= 0xFBC1; /* XGE | XGFRZ | XGIE */
}
//==============================================================================
void ECT_Init(void)
{
//TSCR2 = 0x07; // prescaller = 128
TSCR2 = 0x00; // prescaller = 1
//--- channel 0 setup ---------------
TCTL1 = 0x00; // timer 7~4 disconnected form output pin logic
TCTL2 = 0x00; // timer 3~0 disconnected form output pin logic
TIOS = 0xFF; // channels 0~7 are output compare
//-----------------------------------
TIE = 0; // disable interrupt from channel 0~7
//---------------------------------
TSCR1 = 0xF0; // enable timer,stop in wait,stop in freeze, fast flag clear
}
//******************************************************************************
#pragma CODE_SEG NON_BANKED
//-------------------------------------
interrupt 8 void TCO_Isr(void)
{
TFLG1 = 0x01; // clear interrupt flag
TIE_C0I = 0; // disable interrupt from channel 0
SET_CPU_PRIORITY(ECT_CH0, 1); // change (decrease) priority level of TCO isr
SET_CPU_PRIORITY(ECT_CH1, 7); // change (increase) priority level of TC1 isr to max value 7
asm PSHCW; // chanage priority level (IPL in CCRW)of current isr on the STACK to 1
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; // clear I bit to make interrupt interruptible (nested interrupts)
function0(); // call function which has to be performed at this moment
}
//-------------------------------------
interrupt 9 void TC1_Isr(void)
{
TFLG1 = 0x02; //
TIE_C1I = 0; //
SET_CPU_PRIORITY(ECT_CH1, 1); //
SET_CPU_PRIORITY(ECT_CH2, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function1();
}
//-------------------------------------
interrupt 10 void TC2_Isr(void)
{
TFLG1 = 0x04; //
TIE_C2I = 0; //
SET_CPU_PRIORITY(ECT_CH2, 1); //
SET_CPU_PRIORITY(ECT_CH3, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function2(); //
}
//-------------------------------------
interrupt 11 void TC3_Isr(void)
{
TFLG1 = 0x08; //
TIE_C3I = 0; //
SET_CPU_PRIORITY(ECT_CH3, 1); //
SET_CPU_PRIORITY(ECT_CH4, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function3();
}
//-------------------------------------
interrupt 12 void TC4_Isr(void)
{
TFLG1 = 0x10; //
TIE_C4I = 0; //
SET_CPU_PRIORITY(ECT_CH4, 1); //
SET_CPU_PRIORITY(ECT_CH5, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function4();
}
//-------------------------------------
interrupt 13 void TC5_Isr(void)
{
TFLG1 = 0x20; //
TIE_C5I = 0; //
SET_CPU_PRIORITY(ECT_CH5, 1); //
SET_CPU_PRIORITY(ECT_CH6, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function5();
}
//-------------------------------------
interrupt 14 void TC6_Isr(void)
{
TFLG1 = 0x40; //
TIE_C6I = 0; //
SET_CPU_PRIORITY(ECT_CH6, 1); //
SET_CPU_PRIORITY(ECT_CH7, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function6();
}
//-------------------------------------
interrupt 15 void TC7_Isr(void)
{
TFLG1 = 0x80; //
TIE_C7I = 0; //
SET_CPU_PRIORITY(ECT_CH7, 1); //
SET_CPU_PRIORITY(ECT_CH0, 7); //
asm PSHCW; //
asm LDAA #1; //
asm STAA 0,SP; //
asm PULCW; //
EnableInterrupts; //
function7();
}
//-------------------------------------
#pragma CODE_SEG DEFAULT
//******************************************************************************
void function0(void) { PORTB_PB0 = 0; for(i0=0;i0<2000;i0++) { asm nop;} again++; }
void function1(void) { PORTB_PB1 = 0; for(i1=0;i1<2000;i1++) { asm nop;} again++; }
void function2(void) { PORTB_PB2 = 0; for(i2=0;i2<2000;i2++) { asm nop;} again++; }
void function3(void) { PORTB_PB3 = 0; for(i3=0;i3<2000;i3++) { asm nop;} again++; }
void function4(void) { PORTB_PB4 = 0; for(i4=0;i4<2000;i4++) { asm nop;} again++; }
void function5(void) { PORTB_PB5 = 0; for(i5=0;i5<2000;i5++) { asm nop;} again++; }
void function6(void) { PORTB_PB6 = 0; for(i6=0;i6<2000;i6++) { asm nop;} again++; }
void function7(void) { PORTB_PB7 = 0; for(i7=0;i7<2000;i7++) { asm nop;} again++; }
//******************************************************************************
// void main(void)
//******************************************************************************
void main(void)
{
//----------------------------------------
SetupXGATE();
//----------------------------------------
ECT_Init();
//----------------------------------------
EnableInterrupts;
//----------------------------------------

DDRB=0xFF;

for(;;)
{
PORTB = 0xFF;
baseTime = TCNT; // get current value of TCNT
again = 0;
// COMPENSATION is get during debugging
TC0 = baseTime + INTERVAL0 - COMPENSATION; //
TC1 = baseTime + INTERVAL1 - COMPENSATION; //
TC2 = baseTime + INTERVAL2 - COMPENSATION; //
TC3 = baseTime + INTERVAL3 - COMPENSATION; //
TC4 = baseTime + INTERVAL4 - COMPENSATION; //
TC5 = baseTime + INTERVAL5 - COMPENSATION; //
TC6 = baseTime + INTERVAL6 - COMPENSATION; //
TC7 = baseTime + INTERVAL7 - COMPENSATION; //

TFLG1 = 0xFF; // clear interrupt flags of channels 0~7
TIE = 0xFF; // enable timer interrupts of channels 0~7
while(again!=8); // wait till entire set of functions is finished
}
}
//******************************************************************************
// Services performed by NXP in this matter are performed AS IS and without any warranty. CUSTOMER retains
// the final decision relative to the total design and functionality of the end product. FREESCALE neither
// guarantees nor will be held liable by CUSTOMER for the success of this project.
// FREESCALE DISCLAIMS ALL WARRANTIES, EXPRESSED, IMPLIED OR STATUTORY INCLUDING, BUT NOT LIMITED TO, IMPLIED
// WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ON ANY HARDWARE, SOFTWARE ORE ADVISE SUPPLIED
// TO THE PROJECT BY FREESCALE, AND OR NAY PRODUCT RESULTING FROM FREESCALE SERVICES . IN NO EVENT SHALL FREESCALE
// BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT.
//
// CUSTOMER agrees to hold FREESCALE harmless against any and all claims demands or actions by anyone on account of
// any damage, or injury, whether commercial, contractual, or tortuous, rising directly or indirectly as a result of
// the advise or assistance supplied CUSTOMER in connection with product, services or goods supplied under this Agreement.
//******************************************************************************

[fanziyu]

thanks for your help!

Now,I can use interrupt nesting function succefully,but something still confuse me.

1: I configurate the hall width timer capture interrupt the highest priority,then i should configurate LIN interrupt, but I found that modifying lin_lld_sci_isr()  is complicated and risky.

I am making a motor project,  the more accurate the Hall pulse width collection, the better，can you give more advice?

[fanziyu]

Thanks for your help!

I will study your answer again when I have more experience.Now i have to complete my project first.

one more problem

1:In mc9s12zvl64 ,how to configurate INT_CFADDR and INT_CFDATAn

example: Timer0Channel4     vector address:vector base + 0x1bc   

My answer:

0x1bc/4 = 0x6f ;

1): 0x6f>>3 = 0xD; so INT_CFADDR_INT_CFADDR = 0xD;

2): 0x6f&0x07 = 7; so INT_CFDATAn  is  INT_CFDATA7 ;  

Is it right? Do I still need to manipulate the stack for interrupt nesting?

2:I worry about the stack size when i enable the interrupt nesting,besides,i have some large array. So could you tell me how to calculate the project stack size used?It will be better to give some reference  document.