S12X output compare

[roberthiebert]

MC9S12XEP100 112LQEP. Programming in assembler.

I want all port P pins to be output compare, but I am having some difficulty in making them work. I suspect it may be something I’ve done in my set up. Does anyone see anything wrong with this?

movb #$FF,DDRP       ; (all port P pins outputs)

movb #$FF,TTIOS       ; TTIOS equ $03D0 (all channels outputs)

movb #$98,TTSCR1   ; TTSCR1 equ $03D6 (timer enabled, no stop in wait,

                                       ; no stop in freeze, fast flag clear, precision timer)

movb #$00,TTOV       ; TTOV equ $03D7 (Toggle OC pin on overflow disabled)

movb #$55,TTCTL1   ; TTCL1 equ $03D8 (toggle output line Ch7,6,5,4)

movb #$55,TTCTL2   ; TTCL2 equ $03D9 (toggle output line Ch3,2,1,0)

movb #$00,TTCTL3   ; TTCL3 equ $03DA (capture disabled Ch7,6,5,4)

movb #$00,TTCTL4   ; TTCL4 equ $03DB (capture disabled Ch3,2,1,0)

movb #$00,TTIE         ; TTIE equ $03DC (interrupts disabled)                                  

movb #$07,TTSCR2   ; TTSCR2 equ $03DD (timer overflow interrupt disabled,

                                       ; timer counter reset disabled, prescale divide by 128)                            

movb #$FF,TTFLG1   ; TTFLG1 equ $03DE (clear all flags)

movb #$FF,TTFLG2   ; TTFLG2 equ $03DF (clear all flags)

movb #$00,PACTL     ; PACTL equ $03F0 (Pulse accumulator disabled)

movb #$02,PAFLG     ; PAFLG equ $03F1 ( Clear pulse accumulator flags)

movb #$00,TOCPD     ; TOCPD equ $03FC (Enable all timer channel pins)              

movb #$7F,TPTPSR     ; TPTPSR equ $03FE (prescale 128, 2.56us resolution,

                                       ; max period 167.7696ms)

Thanks,

Robert

[Fast]

Hi Robert, I missed the boat on this question. Not all S12X have a TIM is it only P types? But the XGATE can make Output Compare channels, much like the PWM app. Do not get greedy use TCNT for synchronisation with ECT, 1us bit time resolution is possible depending on XGATE loading.

[roberthiebert]

Hi Radek,

Ah so! I didn't know that register even existed. Many thanks.

Robert

[RadekS]

Hi Robert,

You are welcome.

Anyway, when you look at Table 2-2. Pin Functions and Priorities in RM, the signals in brackets are routed by default to another pin and you have to modify routing one of the routing registers for enabling this signal on the pin.

Did it work after routing register change?

BR

Radek

[roberthiebert]

Hi Radek,

Unfortunately I 'm still doing something wrong. Here is my initialization and test coding:

;*Equates:

PTP               equ $0258

DDRP           equ $025A

PTRRR         equ $036F

TIM_TIOS   equ $03D0

TIM_TCNT   equ $03D4

TIM_TSCR1 equ $03D6

TIM_TCTL2 equ $03D9

TIM_TIE       equ $03DC

TIM_TSCR2 equ $03DD

TIM_TFLG1 equ $03DE

TIM_PTPSR equ $03FE

TIM_TC3     equ $03E6

;*Port P and TIM initialization:

   movb #$FF,PTRRR         ; all TIM1 OC channels available on Port P

   movb #$FF,DDRP         ; all pins outputs

   movb #$00,PTP               ; initialize all pins low

   movb #$FF,TIM_TIOS   ; all channels outputs

   movb #$88,TIM_TSCR1 ; timer enabled, no stop in wait, no stop in freeze, no fast flag    

                                             ;clear, precision timer

     movb #$FF,TIM_TIE     ; enable interrupts all channels

     movb #$07,TIM_TSCR2 ; timer overflow interrupt disabled, timer counter

                                               ; reset disabled, prescale divide by 128                              

     movb #$FF,TIM_TFLG1 ; clear all flags

     movb #$80,TIM_TFLG2 ; clear TOF flag

     movb #$7F,TIM_PTPSR ; prescale 128, 2.56us resolution, max period 167.7696ms

;*Test code to set channel pin high after ~2.56Usec:

   movb #$08,TIM_TFLG1   ; clear Ch3 flag

   movb #$C0,TIM_TCTL2   ; Set Ch3 output line to 1 on compare)

   ldd TIM_TCNT                 ; Contents of Timer Count Register-> Accu D

   addd #$0001                       ; Add 1 (2.56uS)

   std TIM_TC3                     ; Start OC operation

                                                ; Should result in pin high and interrupt in ~2.56uS

;*SUCSESS, PIN HIGH!                      

;*Test code to set channel pin low after ~168Msec (TIM Ch3 Interrupt Service Routine)

   movb #$08,TIM_TFLG1 ; clear Ch3 flag

   movb #$80,TIM_TCTL2 ; clear Ch3 output line to zero on compare

   ldd TIM_TCNT       ; contents of Timer Count Register-> Accu D

   addd #$FFFF           ; add 65535 ~168Msec

   std TIM_TC3         ; start OC operation

                                    ; Should result in pin low in ~168Msec

;*NO SUCSESS!

I'm still worrying away at it, but do you see anything obvious?

Thanks,

Robert

[RadekS]

Hi Robert,

When you use fast flag clear, you should avoid manual flag clearing.

The flags will be automatically cleared by writing into TC1..TC7 registers (which missing in your code).

The ECT timer module is rather designed for interrupt driving.

Below is very simple ECT example code in C-language for your reference.

#define ECT_PERIOD 500  //500us

//==============================================================================
//TC0_ISR
//==============================================================================
#pragma CODE_SEG NON_BANKED
interrupt 8 void TC0_ISR(void)
{
ECT_TFLG1 = 0x01;             //clear the flag    
ECT_TC0 = ECT_TC0 + ECT_PERIOD;}
#pragma CODE_SEG DEFAULT

//==============================================================================
//Timer_Init
//==============================================================================
void ECT_Init(void)
{
//timer clk = bus clk / prescaler = 8Mhz / 8 = 1MHz       
ECT_TIOS = 0x01;    //channel 0 as output compare  
ECT_TIE = 0x01;     //interrupt enable  
ECT_TSCR2 = 0x03;   //prescaler = 8  
ECT_TC0 = ECT_PERIOD;   
ECT_TCTL1 = 0x00;  
ECT_TCTL2 = 0x01;   //output compare action - toggle channel 0  
ECT_TSCR1 = 0xA0;   //timer enabled}

//==============================================================================
//main
//==============================================================================
void main(void) 
{
  ECT_Init();    
  EnableInterrupts;      
  for(;;) 
  {
  }
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I hope it helps you.

Best regards

Radek

[roberthiebert]

Hi Radek,

Thanks for your response. Unfortunately my knowledge of "C" is very limited, but I think I understand what your code does. I forgot to mention that I am using the TIM module, not the ECT module. I think they are quite similar in output compare operation though. I hadn't included my operation test code, just the init code to see if I had the set up correct or not. To test the code I have the PP0 (S12X pin 4) controlling an NPN transistor which controls an LED. The LED lights up when the pin goes high. To test it I add 65535 to the current value in TCNTH and load it into TTC0. This should give me a ~168Ms off delay. The LED lights up alright, but no matter what code changes I make, it will not time off.

bset  PTP,PP0

ldd   TCNTH

addd #$FFFF

std   TTC0

I have the interrupts disabled, is it still necessary to clear any interrupt flags either manually or by fast flag clear?

Also, is there someplace in the manuals that gives a list of the various register states out of reset?

Thanks,

Robert

[roberthiebert]

Hi again Radek. This is embarrassing! Disregard the question of reset states. I just found them in each register description. The other issues remain, unfortunately.

Regards,

Robert

[RadekS]

Hi Robert,

Thank you for clarification of your test environment. And especially for note about TIM.

Yes, you are right, the TIM and ECT modules are more-less the same. ECT has just some additional features.

Two notes:

• TCNTH is typically name for upper byte from TCNT register.
• The TIM is by default routed to the port R (available only on MAPBGA package). You may route TIM signals to the port P by editing PTRRR Please check whether you configured this register correctly.

BR

Radek