S12X 8-bit external RAM

[gravity]

Hi,

We wish to use an 8-bit RAM device externally on a S12XDP512. What needs to be done to wire this up, and what needs to be done so that we can do 16-bit access to this device?

I'm guesssing that its' not possible? Even though the top half of the data bus can be disabled, the MCU does'nt sequence 16-bit accesses?

Thanks

[gravity]

Thanks for that,

A second question, on behalf of our hardware engineer.

We wish to use a 3.3V SRAM, but run the micro at 5V. There is a bit in the EBI that enables 3.3V thresholds for the external bus. Does the EBI also drive outputs at 3.3V levels?

Cheers

[Steve]

Hi gravity, the reduced input threshold doesn't change the output voltage at all so it will still be 5V. The ITHRS bit only affects the input threshold and is intended for use with 5V tolerant peripherals that are running at 3.3V.

[Steve]

You can certainly connect an 8-bit memory onto the S12X and as you say you can save the unused upper 8-bits of the data bus (and some address lines if needed).

However, since the databus is only 8-bits wide you cannot do 16-bit accesses to it. The main reason is that the S12X does not provide the least-significant address line (A0). Instead it uses upper and lower strobe signals to select which byte to access on an aligned 16-bit address. You can of course do 8-bit accesses.

Note that if you ignore the UDS and LDS signals the CPU would see your data repeated in the upper and lower byte of an aligned 16-bit memory location.

Message Edited by Steve on 04-06-200609:42 AM

[imajeff]

Steve, you indicate that S12X has no way to do a 16-bit access on the 8-bit external memory. Do you mean one cannot use a 16-bit instruction, or can the instruction access the 16-bit value in two access cycles, like it does on HC12?

[Steve]

Hi, the difference for S12X is that it always operates as a 16-bit data bus, thus:
The 16-bit data interface implements the byte-access/misaligned-word access by driving the word-aligned address (e.g. 0x401000) and using the LDS and UDS strobes to pick off either the upper- or lower-byte as required. In this way you can do byte reads and word reads starting at any address in memory (the byte at 0x401000 is read by asserting UDS and driving 0x401000 onto the bus). A misaligned word access (say to 0x401001) would use two consecutive reads at 0x401000 then 0x401002 and select the correct byte by asserting firstly LDS (for 0x401001) and then UDS (for 0x401002). So a 16-bit memory is completely supported for accessing any word or byte anywhere.
The limitation with 8-bit data busses is that S12X only delivers these word-aligned addresses to the peripheral (Notice in the above example that S12X never provides the address 0x401001). So accessing a byte is no problem but attempts to do 16-bit accesses will only work for the odd byte of the word access.
Hope that's clear - it's a bit complicated to explain in a text format, but Daniel covers the 8-bit options very well in AN2708 on page 9.
Cheers,
Steve

Message Edited by Steve on 04-06-200610:22 PM

[imajeff]

Yes I think you explained it good now.

In summary,

If I were to attach an 8-bit RAM device, it would be easy enough except that my program would only see RAM at every other byte location, or even same one at even and odd bytes depending on how I use LDS and UDS.

So I might have:

0x401000 RAM byte 0
0x401001 [undefined]
0x401002 RAM byte 1
0x401003 [undefined]
...

[Steve]

Hi,

 It depends on how you wire up the addresses but let's say you wire A1 to A0 on the RAM, A2 to A1 etc. In this case you would get:

0x401000 [undefined]

0x401001 RAM byte 0
0x401002 [undefined]
0x401003 RAM byte 1

 My comment in the original reply about the effect if you "ignore UDS and LDS" was misleading. If you disable the upper data bytes the UDS and LDS signals are disabled and you get the above effect. Sorry about the confusion - I was trying to convey the situation where external logic could allow the user to ignore the effect of  the strobes.