Hi,
The signals at PT1/2/3 have to reach V_IH, V_IL (Table A-12, #1-5, S12ZVM RM) to be detected.
Also, the IC1 interrupt has the second highest priority (5) after ADC0_done (6), as per MTRCKTSBNZVM128 source code. If there is ADC0_done ISR in progress, IC1 interrupt must wait.
Regards,
Daniel