void READ_FUEL_GAUGE (byte cmd) {MSBYTE = 0xAA;LSBYTE = 0xAA;SLAVE_ADDR = 0xFF;__asm BSET IBCR,#$80; //enables IIC__asm BSET IBCR,#$30; //enables master transmit mode__asm MOVB #$40,IBFD; //sets freq to 100 kwhile ((IBSR & 0x20) == 0x20); //while bus is busy....__asm MOVB #$8E,IBDR; //initiate start/slave addresswhile ((IBSR & 0x01) == 0x01); //wait for ackwhile ((IBSR & 0x20) == 0x00); //wait to ensure we have the buswhile ((IBSR & 0x02) == 0x00); //ensure previous byte is done__asm BSET IBSR,#$02; //clear the flag__asm MOVB cmd,IBDR; //send bytewhile ((IBSR & 0x01) == 0x01); //wait for ackwhile ((IBSR & 0x02) == 0x00);__asm BSET IBSR,#$02;__asm BSET IBCR,#$04; //restart signal__asm MOVB #$8F,IBDR; //initiate start/slave addresswhile ((IBSR & 0x01) == 0x01); //wait for ackwhile ((IBSR & 0x02) == 0x00);__asm BSET IBSR,#$02;__asm BCLR IBCR,#$10; //sets master rcv modeSLAVE_ADDR = IBDR; //why do i get slave addr here—–˜while ((IBSR & 0x02) == 0x00); //had these before__asm BSET IBSR,#$02;__asm BSET IBCR,#$08;LSBYTE = IBDR;while ((IBSR & 0x02) == 0x00);__asm BSET IBSR,#$02;__asm BCLR IBCR,#$20; //initiate stop conditionMSBYTE = IBDR;__asm BCLR IBCR,#$80; //turn off IIC}
Message Edited by Alban on 2006-11-05 11:26 AM
Hi timmy10ar
Below I have sent you some pseudo code taken from a project which is reading things like temperature sensors and RTCs over the I2C bus. It is a M9S12NE64 but it looks as though the I2C controller is compatible with the one in your chip.
It is interrupt driven but the flow should be much the same as yours using polling. It is basically C-code but should be easily interpretable in assembler.
Perhaps you see something which is different?
Regards
Mark Butcher
www.mjbc.ch / www.uTasker.com
Configuration
{
IBFD = 0x89; // set IIC bus frequency
IBCR = (IBEN); // enable IIC bus
IBCR = (IBEN | MS_SL); // enable IIC bus in master mode
}
// Start command write
{
IBCR |= (MS_SL | TX_RX | IBIE); // generate start condition / enable IIC interrupt
IBDR = (ucAddress); // send the slave address
}
// on each tx interrupt (during tx phase)
IBSR |= IBIF; // clear the interrupt flag (by writing a '1')
if first interrupt
IBDR = cmd; // send command byte
else if second interrupt
IBCR |= RSTA; // restart since we are hanging a second telegram on to previous one
IBDR = (ucAddress | 0x01); // send the slave address
}
// On each interrupt (during read phase)
{
IBSR |= IBIF; // clear the interrupt flag (by writing a '1')
if first interrupt
IBCR &= ~TXAK; // ensure we acknowledge multibyte reads
IBCR &= ~TX_RX; // go to master receive mode
ucRx = IBDR; // dummy read
return
else if last but one byte
IBCR |= TXAK; // we don't acknowledge last byte
else if very last byte
IBCR &= ~MS_SL; // send end condition
IBCR &= ~(IBIE); // disable interrupts
*IIC_rx_control->IIC_queue.put++ = IBDR; // put received byte into input buffer
}