Hi Yosuke,
In case of RISC architecture the MIPS value means that the device runs with a bus cycle and that executes a single instruction for a single bus cycle.
However, the best value that can give you more of reference is the Max Bus Frequency rather than the MIPS.
In the case of S12(X), the architecture of devices make that the instructions take different time to execute. Some instructions take 1 bus cycle, other can take more than 5 bus cycles depending on the complexity of the instruction. So it's not very easy to just list a value to evaluate the CPU performance (MIPS value).
But if you want to check the execution time of HCSx12 instruction, you can find the information in Table A-2. of S12XCPURM at http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf which can give you a more precise execution time for each instruction. For example, INCA needs 1 bus cycle while EDIV needs 11 bus cycles, which means the MIPS value for INCA would be 25 and EDIV is about 2.5 while CPU works at 25MHz Bus Frequency.
So for example:
- the S12P line max bus freq is 32MHz;
- the S12G line max bus freq is 25MHz;
- the S12XE line has maximum bus clock frequency at 50MHz, plus XGATE RISC coprocessor core which can give up to 80MIPS, so all in all, theoretically around 100MIPS.
More comparison between various S12(X) families you can find here:
http://cache.freescale.com/files/microcontrollers/doc/support_info/MC9S12_X_CORE_DIFF.pdf
Hope the info helps.
Regards,
iggi
