Hi jy1,
In my opinion those aspects needs to be taken into consideration:
1) ADC input voltage limit : output of the voltage divider must not exceed allowed limit for ADC pin when maximum voltage appears on VBAT.
VBAT*R2/(R1+R2) < limit
2) Acceptable power dissipation on voltage divider P=(VBAT^2)/(R1+R2) for your application.
3) R1, R2 and C will create a filter. Filter shouldn't distort useful signal (for example if VBAT ripple needs to be measured it shouldn't filter it) or it shouldn't increase overvoltage detection time over what is acceptable for your application.
4) Capacitor C will act as a supply for internal sampling circuit (internal resistance and sampling capacity). Energy will flow from C capacitor to sampling capacitor and it shouldn't create voltage drop that is out of acceptable value for your application.
Characteristics of S12ZVL internal sampling circuit can be found in MC9S12ZVL Family Reference
Manual and Datasheet.
Best regards,
Tomas Fedor.