I am using the 144 pin MC9S12XEP100.
PORTC pins do not work when set as outputs and toggled. They just stay on 5 volts all the time. Adding a 10k pullup makes no difference.
Other port pins like PORTD work as expected. I looked at the datasheet to see if PORTC has some other function that I need to turn off. I could only find this. What am I missing ?
126.96.36.199 PC[7:0] / DATA [15:8] — Port C I/O Pins
PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allowdata from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are
configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds
for PC[7:0] are configured to 5-V levels out of reset in normal modes.
There are some differences between the ports according to CPU12X reference manual.
Refer to core reference manual in following text:
“Access Detail” for BSET instruction is rPwO (see page 139). Each single letter represents one bus cycle. However, this is only the best case. This instruction will take 4 bus cycles or more – it depends on the memory which is accessed by this instruction.
The description of cycle code letters can be found on pages 80-82. For example, first letter “r” is described as:
r — 8-bit data read. These cycles are stretched only when controlled by a chip-select circuit programmed for slow memory.
So, there can be some stretching depending on address.
The port registers related to external bus interface (port A, B, C, D, E, K) are slow, so the instruction which access these ports will take more time. BSET or BCLR will take 6 cycles. If you use exactly the same instruction (the same opcode) just with address different from port A, B… then you can reach 4 bus cycles execution time.
Note: BSET instruction on port A is 2 cycle longer because BSET contains read and write operations (both are slow at external interface ports). For example LDAA contains just read operations and therefore LDAA on port A will be 1 cycle longer than LDAA on port M (4/3 cycles).
Note: Duration of every instruction you can check in Full Chip Simulation. See Register window-CPU Cycles: .
Note: How simply distinguish between slow and fast port? In default mc9s12xep100.h file, slow ports are marked as PORTx and fast ports as PTx.
Note for DDRM register: “Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. “
Therefore I suppose that data flow between “fast” ports and registers need additionally 1 bus clock (due to internal synchronization circuits).