Hi
Question1:e6181 workaround: The ADC should not be disabled before any flow control request (SEQA,TRIG,RSTA)is finished(all flow control bits are cleared).
so
ADC0CTL_0_ADC_SR = 1;//execute ADC soft-reset(SR),ADC enters IDLE state
while(ADC0STS_READY == 0){}
ADC0CTL_0 = 0X00;//ADC is disabled
or
ADC0CTL_0_ADC_SR = 1;
while(ADC0STS_READY == 0){}
ADC0FLWCTL = 0X80;//need?
while(0 != ADC0FLWCTL ){}//need?
ADC0CTL_0 = 0X00;//ADC is disabled
Are both the programs correct?
Question2:ATD clock Frequency is 3MHz.10 bit resolution .Then one conversion time ?
if CSL with 17 command entries,then how much time it will cost toally? more details see attachment
thanks!
Hi,
As the workaround for e6181 states,
“It is recommended to issue a Sequence Abort Request and to poll bit SEQA to be clear before ADC is disabled via bit ADCEN.”
ADC0FLWCTL_SEQA = 1; // Issue a Sequence Abort Request
while(ADC0FLWCTL_SEQA){} // Wait until aborted
ADC0CTL_0_ADC_EN = 0; // Disable ADC
The conversion time was discussed in this thread:
S12ZVLA ADC sampling time
Regards,
Daniel
thans for your help.Daniel.I wonder if adc is in idle status,i still have to issue a Sequence Abort Request?
ADC0CTL_0_ADC_SR = 1;//execute ADC soft-reset(SR),ADC enters IDLE state