FAQs
English (US) 日本語 | Japanese 中文 | Chinese (Simplified)

Multiple Interrupt

cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Multiple Interrupt

‎03-06-2023 01:34 AM
814 Views
kathi
Contributor I

Hi team, 

When a double bit RAM/EEPROM error occurs the CPU will enter into machine exception ISR, After entering the Machine Exception ISR I am calling the another interrupt SCI0 ISR for communication but communication is not happening.

Question: How does CPU reacts while handling multiple interrupts at a same time with different priorities .

0 Kudos
Reply
1 Reply

‎03-06-2023 04:22 AM
796 Views
lama
NXP TechSupport
NXP TechSupport

Hi,

The machine exception is not from the set of I-bit maskable interrupt which are interruptible by clearing I-bit inside the interrupt routine.
This is from the set of HW interrupts which are not interruptible.

You did not mention the MCU you are using. If you use MCU from S12Z family devices then you can get more info in the chapters:
4.4 Functional Description
4.4.1 S12Z Exception Requests
4.4.2 Interrupt Prioritization
( https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/MC9S12ZVMRM.pdf )

If you use s12X device you can read: https://www.nxp.com/docs/en/application-note/AN2617.pdf

Best regards,

Ladislav

0 Kudos
Reply