Mapping PIT hardware trigger signals - Can't find the SoC Guide for xep processor.

[Pedro_]

Hi all,

The s12xep100 Reference Manual mentions 8 hardware trigger lines in the PIT module.

The System on Chip Guide should detail which peripheral modules are mapped to this lines, however, I haven't been able to find this guide.

Do you know if that document is available?

Thanks again.

Pedro.

[Steve]

The "SoC guide" is actually chapter one of the manual. You'll find the details of the use of the PIT as a hardware trigger there but it's written from the point of view of the peripheral rather than the PIT (actually the ATD peripherals).

[Pedro_]

That answers my question, Steve, thanks.

I am falling short with the max. underflow time for the ECT Modulus Down Counter and I was wondering if I could latch the accumulators using those triggers .. It was a long shot anyway.

I could always force latch (ICLAT) from the PIT interrupt vector, but then I have to consider if latancy is going to be an issue for me.

mm .. I need etpus !!

Thanks again