> Another example of dumb, useless things is the tx priority register.
Yes, agreed. It won't send them with "the proper priority". You can assign priorities yourself to try and get different IDs going in the right order, but it is a pain.
It is often more important (when sending diagnostic or debug messages) to have them send in the right order, rather than in a priority order based on the IDs. Some protocols use a range of IDs where the lower bits are the "message counter number", so they have to be sent with the priority based on the ID ignored.
> If priorities are equal, the tx buffers will work as a FIFO
Wrong. They don't. A FIFO implies the last one you push in is the last one to go out. It would be very nice if it did work like a FIFO, but it doesn't. If you load up Transmit Buffers 1, 2 and 3 in that order (with the same priorities) and leave it alone it will send them in that order. But if you take an interrupt when "1" goes empty, and put another one in there, IT will now be the "highest priority" one and it will go before "3".
So what you have to do is to put your "sequential messages" in with incrementing priorities, until you get to 255. Then you have to wait until they've all been sent, and only then can you "reset the priorities" back to zero and start again.
> Another example of dumb, useless things is the tx priority register.
But it would be far worse if that register didn't exist. At least you can use it to try and work around all the other problems. Without it you could only ever send "one message at a time using one transmit buffer". At least this lets you send them "three at a time", which is another way to use the available hardware.
Don't get me started on FlexCAN though...
Tom