Hello Ian,
Please find below my comments:
What is the architecture of the Vsense input?
[AA] VSENSE and VOPT are inputs with an internal resistive voltage divider.
There is an ESD structure at the pin to protect against ESD/EMC events. This structure has to be protected against surge current the external resistor is there to insure this protection.
Is there any information about how the input current will vary with temperature?
[AA] Yes, the part was tested at Freescale End of Line by adding into the measurement path a perfect 2.2kOhm (by computation). So the leakage current induced into the resistor is bring into consideration into the VSENSE and VOPT gain and offset compensation values. These values are also available across temperature (delta value to room are available into the compensation repository).
There, it is recommended to customer to run calibration of the voltage at room temp to cover the variation of the resistor to its production process. The temperature compensation change will be handled by running a calibration using a linear interpolation of the channel compensation versus temperature.
There you can use the calibration request interrupt that is driven by internal temperature measurement.
If the temperature is also impacting the value of the external resistor, you can run a compensation over temperature or use a computation law that will minimize the error due to the resistor variation.
All of this can be handled through compensation look up table located into the flash and constructed during the initial compensation of the channel at your end of line.
Can the value of the protection resistor be lowered to reduce the offset error?
[AA] The resistor is there into the application schematic to protect the product against ESD and EMC (protecting the ESD structure against surge current). So yes, but this might lower the sustainability of the product to ESD and EMC events.
