Is RAM retention supported in MC9S12G controller?

[ganeshvijayakum]

Hi,

I would like to know if RAM retention mode is supported in MC9S12G micro controller.

If yes please guide me to enable it.

Thanks in advance.

Regards,

Ganesh Vijaya Kumar P

[RadekS · Accepted solution]

Hi Ganesh,

Could you please specify what you exactly mean by RAM retention?

Do you mean RAM retention as special power save mode with RAM is partially disabled?

In that case, no, the S12G doesn’t have any RAM retention mode. At least it is not documented as user accessible feature.

Note: S12G has SRAM – it doesn’t need a periodical refresh.

In fact, the RAM stays active in low power mode (Stop mode) until the voltage at internal voltage regulator is above Power On Reset assert level (VPORA). This value isn’t specified, it is not accessible from external pins, but POR assert happened typically at approximately around 1.1~1.2V at VDDR.

So, we guarantee that RAM content stays unchanged in low power mode until the voltage is above POR level voltage.

Note: Low voltage reset monitor isn’t active in Stop mode.

Or do you mean some technique for save RAM content into non-volatile memory like Flash/EEPROM?

I hope it helps you.

Have a great day,
Radek

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[ganeshvijayakum]

Hello Radek,

Thanks for your valued answer, could you please guide me from where can I get the SRAM minimum and maximum operating voltages.

I appreciate if you can provide me the documents regarding the FLASH and RAM implementations in S12G micro.

Regards,

Ganesh Vijaya Kumar P

[RadekS]

Hi Ganesh,

As I mentioned, minimum voltage for keep RAM content in Stop mode is not directly specified.

The RAM is powered by internal core voltage. This internal core voltage is monitored by POR reset monitor and when voltage fall below such unspecified value, it will generate POR reset. Since these voltage and monitor signals are not user accessible, we do not specify any levels.

According to our measurement on the desk, the POR reset appears typically when VDDR fall below approximately 1.1~1.2V.

Out of stop mode, the lowest VDDR (VDDX) voltage is specified by Low voltage reset (around 3.02V). See A.12 Electrical Specification for Voltage Regulator in RM for more details.

Note: The system resets (like LVR or watchdog reset) will not affect the RAM content. However, the standard startup code will reinitialize RAM content. If you do not want to initialize some part of RAM during MCU startup, please create user segment and use NO_INIT instead READ_WRITE qualifier in your prm linker file.

The maximum VDDR (VDDX) voltage is specified as 5.5V. See A.12 Electrical Specification for Voltage Regulator in RM for more details.

I hope it helps you.

Have a great day,
Radek

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------