Interrupt priority level assignment : MC9s12xEP100

[lak]

Hi,

I have a question on assigning priority levels to interrupt sources on MC9s12xEP100.

The datasheet describes as below

Interrupt Request Configuration Address Register (INT_CFADDR)

INT_CFADDR[7:4]

— These bits determine which of the 128 configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.

INT_CFDATA0–7

Interrupt Request Configuration Data Registers (INT_CFDATA0–7)

The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data registerof the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively.

Now, does this mean that I will be able to assign priority levels to only those succesive 8 channels starting at that block address contained in INT_CFADDR (ex: vector base + E0)?

If so, then how can i assign priority levels to any eight interrupt sources which are spread out in the vector map and need not be continous?

please advice.

with regards,

Lak

[CompilerGuru]

>Now, does this mean that I will be able to assign priority levels to only those succesive 8 channels starting at that
>block address contained in INT_CFADDR (ex: vector base + E0)?

No, the text mentions 128 :smileyalert: configuration data registers. You can configure all of them, just you have to set INT_CFADDR if you are switching to a channel which is not in the currently visible group in INT_CFDATA. For simplicity, I would just set INT_CFADDR every time before accessing INT_CFDATA. INT_CFADDR just controls which of the 128 registers are currently accessible via the memory interface, it has no effect on the content of the registers.

Daniel

[lak]

Yes, I got it now. I was messing up with the documentation wondering how would these priority levels stay intact with each interrupt source since there are only 8 memory mapped INT_CFDATA registers.

Now that you mentioned them as means to access the internal 128 individual configuration registers, I am clarified.

Thank you.

with regards,

Lak