Help needed for project

[rayhall]

I am looking for someone to help get the S12XE hardware functions setup. I am willing to pay for this to be done. I would like to do it in three stages.This will let me write other code and test before moving on.

Stage One:

  1. Setup S12XE for 48 Mhz

  2. Setup XGate

  3. Setup SPI

  4. Setup SCI with interrupt on RX

  5. Setup ADC

Stage Two:

  1. Setup ECT for input capture on two pins.

  2. Setup ECT for output compare on six pins.

  3. Setup PIT for overflow interrupt

Stage Three:

  1. Setup PWM

  2. Setup CAN 

If you are interested let me know.

Ray,

[RadekS]

We (Freescale technical support) can provide example codes for all your points - for free.

In some cases we can modify example codes directly according your demands.

Unfortunately we are not authorized to build your final application.

[rayhall]

Radek,

Example code would help. What I need is for someone to tell me if how I have used the code from examples are correct. There are things I do not know, if are needed or correct. Example what is this...

#pragma push

/* this variable definition is to demonstrate how to share data between XGATE and S12X */

#pragma DATA_SEG SHARED_DATA

volatile int shared_counter; /* volatile because both cores are accessing it. */

/* Two stacks in XGATE core3 */

#pragma DATA_SEG XGATE_STK_L

word XGATE_STACK_L[1];

#pragma DATA_SEG XGATE_STK_H

word XGATE_STACK_H[1];

#pragma pop

I also found a example with a different version of this..

#pragma push

#pragma DATA_SEG xstack13Seg

uint xgstack13[1];

#pragma DATA_SEG xstack47Seg

uint xgstack47[1];

#pragma pop

So which one is correct and what does this code do.

I do not want someone to build my project. What I want is some help to get the hardware setup.

Also my post looks like it was removed from public view. Why was this done.

Ray.

[RadekS]

I prepared for you compilation of example codes.

https://community.freescale.com/docs/DOC-95116

Not all example codes are directly for S12XE family however peripherals are typically the same.

I hope it helps you.

[rayhall]

Radek,

Thank you very much for this. I still have questions...

In the XEP100 - SCI default - CW47 example the interrupt for the SCI has this code.

#pragma CODE_SEG NON_BANKED

interrupt 20 void SCI0_Isr(void) 

{

}

What is the 20. Is this a interrupt vector number ?

If it is, then where can I find a list of all the interrupt numbers ?

Ray.

[RadekS]

Interrupt number 0 presents POR reset vector, 1 is CM reset, 2 is COP reset, … , 119 is Spurious Interrupt.

Interrupt number = (0xFE-Vector Address)/2.

See Table Interrupt Vector Locations at RM (Table 1-14, page 81-84).

For Example: Interrupt number of SCI0 = (0xFE-D6)/2 = 0x14 = 20.

[rayhall]

Okay I found them in the MC9S12XET256.h file.

Ray.

[RadekS]

This code looks strange, however it is “simple”

#pragma push saves the current state of all the settings imposed via pragmas. Restore these settings by a subsequent #pragma pop. Any changes to the states that occur between a #pragma push and a #pragma pop will be discarded after the #pragma pop.

So, it is nothing special. In this case we can use #pragma DATA_SEG DEFAULT at end of this code. It will do the same (just restore variable placement back to default RAM).

XGATE in version 3 has two hardware sets of basic registers and this way naturally support interrupt nesting. Interrupts with priority 4..7 could interrupts routines with priority 1..3. XGATE simply switch register sets.

For these two sets we should define also two stacks and this is done by this code.

This code just creates two variables at specific location (in default project at 0xF8107E and 0xF810FE addresses, see prm file), nothing else.

More important is this code:

  XGISPSEL= 1;

  XGISP31= (unsigned int)(void*__far)(XGATE_STACK_L + 1);

  XGISPSEL= 2;

  XGISP74= (unsigned int)(void*__far)(XGATE_STACK_H + 1);

  XGISPSEL= 0;

This way we define initial address of stacks for routines with priority 1..3 and for routines with priority 4..7. Every time a thread of such priority is started, RISC core register R7 will be initialized with the content of XGISP74 or XGISP31.

So, I suppose that both codes in your post do the same work however second code uses non-default linker definition in prm file. That is all.