FLASH

[jamska]

On the MC9S12B128 processor, how many times can the 512 byte sector from $4000 to $41FF be erased and written before the FLASH is worn out?

[kef]

See A.3.2 NVM Reliability in MC9S12B128 Device User Guide

It is 10000 cycles at temperatures < 0C, and 100000 at temps > 0C.

[jamska]

100K might not be enough cycles -- app would hit 100,000 in 8 years.  All I really need is 512 bytes (minimum for sector erase).  This chip says it has 1K of EEPROM that triples the cycles rating, but I could not figure out where they put that 1K space.  Once I find it, would I erase and write to it like I do to FLASH at $4000 ?  The documentation of the EEPROM seems to be the same as that for FLASH.  And I saw one reference to a FLASH cycle counter, but can't find it anywhere -- I figured it should be in the FLASH register section...

[kef]

100k is indeed enough. You have lots of sectors. Instead of using one sector, you may use two or more sectors. You find blank sector (all 0xFF) in your set of data sectors and use it to store your data. Next time you use another blank sector. When you are out of blank sectors, you erase them all and start from scratch...

In case you data is N times smaller than sector size, you use one sector and divide it into records. You find blank (all FF) record and fill it, .. when all records are non blank, you erase sector. Again 100k cycles limit, but you may write up to N*100k times.

There's no flash cycle counter. In case you need it, you need to maintain it in your SW.

CPU local address of EEPROM is defined by INITEE register. You need to initialize it to map EEPROM to address you want. B128 device guide states that on reset INITEE is initialized with 1, which means that EEPROM is enabled and mapped to zero address. RAM is also mapped to 0, and since it is higher priority memory, EEPROM is not accessible until you remap either RAM or EEPROM to different address.

[jamska]

Can I set INITEE such that my current FLASH location at $4000 becomes EEPROM?  If so, what setting for INITEE?  And do I erase and write to it the same as I currently do to FLASH? 

[kef]

• Can I set INITEE such that my current FLASH location at $4000 becomes EEPROM?  If so, what setting for INITEE? 

Yes, INITEE = 0x41. 0x40 for address 0x4000 and 1 for EEPROM enabled.

• And do I erase and write to it the same as I currently do to FLASH?

Though erase and write algorithms are similar, EEPROM uses different set of control registers (ECLKDIV instead of FCLKDIV, ESTAT instead of FSTAT, etc). Also EEPROM erase sector size is much more smaller. It is just 4 bytes. So you need to edit your flash routines to make them working with EEPROM.

[jamska]

Where can I find a document on EEPROM and how to use it?

[kef]

Complete S12B documentation is here:

http://cache.freescale.com/files/microcontrollers/doc/data_sheet/9S12B128_ZIP.zip

EEPROM documentation is in B128\S12EETS1KV1.pdf

[jamska]

I will stick with FLASH, and using your first suggestion of opening a new sector each time an old sector wears out.  The trick here is detecting when it is time to move to a new sector.  Temperatures at operation are uncontrolled (outdoor product), so the number of cycles to end of life is variable in the range of 10,000 to 100,000 -- big range.

When FLASH "wears out", what is the mechanism of failure?  Does it refuse to erase completely?  If so, is a second erase OK?  Or does it refuse to write zeroes? 

Whatever I design will be virtually untestable.  At 30 milliseconds per erase/write (512 bytes), it would take 50 hours to get to 100,000 cycles, and when it gets there, it might still be working, or a failure might cause the processor to fail.  I dunno.

[kef · Accepted solution]

Suggestion was not to change sector when flash wears out (bad idea), but write each time to different sector, so that each sector from a set of sectors is cycled +-1 the same number of times. If you need guaranteed 200k writes even at low temps with specified 10k limit, then you should use at least 200k / 10k = 20 sectors. You write to 1st sector, then write to 2nd, etc. When you are about to write 21st sector, you erase all 20 sectors and write data to 1st sector and so on.

• When FLASH "wears out", what is the mechanism of failure?  Does it refuse to erase completely? 
• If so, is a second erase OK?  Or does it refuse to write zeroes? 

I never met this kind of failure, but I think it may both either refuse to erase or refuse to program some bits.

[jamska]

Your suggestion to erase a large chunk (like 8K) and incrementally write to it would work great.  However, I was not able to figure out what is needed to get an 8K erase from $4000 to $5FFF.  This is what I am doing now to erase 512 bytes from $4000:

        ldaa     FSTAT

        staa     FSTAT

        movb   #%01001111,FCLKDIV      ; 24.576 MHZ osc.

        movb   #$3E,PPAGE

        ldaa     #$0

        staa     FCNFG

        ldx        #$4000

        std        ,x

        ldaa     #$40

        staa     FCMD

        jsr        DoOnStack       ; execute FLASH command from RAM

What should I do to erase 8K?

[kef]

Yes, you should erase 8k sector by sector.

        ldaa     FSTAT

        staa     FSTAT

^^ this is wrong. Above these two commands, CBEIF is most likely set, so you are making an attempt to launch flash command! Clear just error flags, but not CBEIF.

        movb   #%01001111,FCLKDIV      ; 24.576 MHZ osc.

^^ Is 24MHz your crystal or external oscillator clock, not bus clock? For old S12 parts (not new like S12P), you should use your external crystal/ oscillator clock to calculate FCLKDIV.

        movb   #$3E,PPAGE

^^ this is not necessary when you are writing to 0x4000.

        ldaa     #$0

        staa     FCNFG

        ldx        #$4000

        std        ,x

        ldaa     #$40

        staa     FCMD

        jsr        DoOnStack       ; execute FLASH command from RAM

[jamska]

OK on all.  Everything now working.

Is    bclr  FSTAT,%00110000    what you were thinking?

24.576 is crystal and bus clock (after PLL doubler).

PPAGE stays at 3E anyway.

What is an S12P processor?

[kef]

Forgot to comment this:

• Is    bclr  FSTAT,%00110000    what you were thinking?

This is again wrong. What does BCLR? It reads byte from FSTAT (say it was 0xA0) , clears specified bits in byte (0xA0 & ~0x30 = 0x80), and writes result back to FSTAT. Instead of clearing error flags this is again an attempt to launch flash command. You need to

   BCLR FSTAT, #~0x30

or

   BCLR FSTAT, #0xCF

or just

   MOVB  #0x30, FSTAT

[jamska]

I like MOVB ... done.

End of thread.  (sad)  Thanks for all the help. 

[kef]

• 24.576 is crystal and bus clock (after PLL doubler).

you should use crystal clock to calculate FCLKDIV, not PLL and not the bus clock.

S12P:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=S12P

[jamska]

For the S12P processors, can you point me to a schematic for the external filter for the PLL, and the calculation of the resistor(s) and cap(s) ?

[kef]

S12P has internal PLL filter

[jamska]

I figured it out -- must erase 512 bytes at a time, $4000, $4400, $4800, etc., until all is erased.