Hello to the entire community. First of all, I apologize for my English; some of it is mine and some is from Google.
I'm working on a low-level development. I'm appealing to those who have been programming in assembler for a long time, although a good explanation from anyone who understands it will be helpful.
My program is small, only about 8KB of program and 7KB of RAM, but it required the resources, power, and speed of this dual-core. I have some parameters that can be changed by configuration and must be used in EEE.
For this reason, I need to understand a few things:
I've searched the forum and haven't found anything that clarifies the situation.
Where is the buffer RAM defined? Does it use non-paged memory by default, or can I choose it?
Similar question with the EEPROM (D-Flash). Can I choose which D-Flash page to use for EEE or does it use non-paged?
When partitioning, I can't tell it the global address it should use.
I've read the application notes AN3490, AN3743, and Chapter 27 of M9S12XEP100RMV1 where it talks about the 512 Kbyte flash module (S12XFTM512K3V1), since I'm using an XEQ512. I also downloaded the AN3743SW software and don't fully understand it. I mean, I understand it when I read it, but my question is the one I already mentioned.
I would appreciate any help.
Solved! Go to Solution.
Hi,
Where is the buffer RAM defined? Does it use non-paged memory by default, or can I choose it?
Similar question with the EEPROM (D-Flash). Can I choose which D-Flash page to use for EEE or does it use non-paged?
When partitioning, I can't tell it the global address it should use.
1) If I consider DFLASH is used as a standard EEPROM. In this case you have to E/W is as standard flash and you are responsible for erasing sectors to be written and also all logic related to E/W.
2) If I consider entire buffer RAM is used with entire DFLAH to create EEEPROM then I use buffer RAM as standard RAM space and all E/W processe are ensured by internal EEPROM machine. The buffer RAM can be seen in the attached memory map. It can be used as standard RAM if EEEPROM is not used. The buffer RAM can be accesses by near address but only part of it (0C00~0FFF). Fully accessible is via global address (linearly) or EPAGE_offset based address (not linearly because pages do not consequent from offset point of view)
I forgot I did examples so I attached them here. Both C code and asm code as well.
I do not have memory map prepared for XEQ512 but it is very similar and in the case of DFLASH and EEEPROM the same.
I added buffer ram examples only to show you haw can it be used if it is not used for EEEPROM.
BR,
Ladislav
Excellent! The Excel spreadsheets have been the most helpful to me; the explanation is perfect. And the assembler projects are simple and very understandable.
With such help, I'll soon share with you a routine and macro I designed to handle all Flash commands in assembler with just one call to the command and its parameters; detecting invalid commands, missing parameters and data, etc.
Best regards, and thank you very, very, very much.
Thanks for your quick response, thank you very much, I'll run some tests and report back.
Hi,
Where is the buffer RAM defined? Does it use non-paged memory by default, or can I choose it?
Similar question with the EEPROM (D-Flash). Can I choose which D-Flash page to use for EEE or does it use non-paged?
When partitioning, I can't tell it the global address it should use.
1) If I consider DFLASH is used as a standard EEPROM. In this case you have to E/W is as standard flash and you are responsible for erasing sectors to be written and also all logic related to E/W.
2) If I consider entire buffer RAM is used with entire DFLAH to create EEEPROM then I use buffer RAM as standard RAM space and all E/W processe are ensured by internal EEPROM machine. The buffer RAM can be seen in the attached memory map. It can be used as standard RAM if EEEPROM is not used. The buffer RAM can be accesses by near address but only part of it (0C00~0FFF). Fully accessible is via global address (linearly) or EPAGE_offset based address (not linearly because pages do not consequent from offset point of view)
I forgot I did examples so I attached them here. Both C code and asm code as well.
I do not have memory map prepared for XEQ512 but it is very similar and in the case of DFLASH and EEEPROM the same.
I added buffer ram examples only to show you haw can it be used if it is not used for EEEPROM.
BR,
Ladislav