Cause of RESET on MC9S12XDP512

[RuiFaria]

Hello,

How could i verify the cause of RESET on MC9S12XDP512?

Best Regards,

Rui Faria

[iggi]

I agree with Edward that you should search for the keyword in the ref. manual, because the information is there.

Anyway, i will point you to the right place. First of all, open the MC9S12XDP512 ref. manual:
http://cache.freescale.com/files/microcontrollers/doc/data_sheet/MC9S12XDP512RMV2.pdf

As you may already know, there are several reset sources. See chapter 2.5 Resets and the Table 2-14. Reset Summary.

The external pin reset, power-on reset (POR), low-voltage reset (LVR) and illegal address reset share the same vector address 0xFFFE.

For that reason, there are flags in the CRG registers: PORF and LVRF in the CRGFLG; ILAF in the CRGINT.

Regarding the Clock Monitor Reset and Watchdog Reset, these two must be enabled in the first place.

Hope the information helps.

Regards,

iggi

[hareeshakoratik]

Hi Rui,

          First, find out is this reset is caused by micro controller itself or it is from external source. If reset is caused by external source, then reset time should be around 4ms.After eliminating one source, concentrate and debug the configurations of caused source.

[RuiFaria]

Hi,

Is it impossible to read one register of cpu to detect the cause?

[hareeshakoratik]

Hello,

          I think no. Reset pin should be high During normal MCU operating condition and it will go low during reset. Measure Reset pin low duration. If this duration is around 4 ms means this reset is caused by outside source or it is caused my MCU itself.

Thanks & Regards,

Hareesha.

[kef2]

It is a good idea to read datasheets sometimes! I invite you both to do so. COP and CME have dedicated reset vectors. The rest of reset sources have corresponding flags. Look for PORF, LVRF and ILAF.

If these flags or COP/CME vectors don't work for you, then you haven't read datasheet and CPU12X RM long enough. Good luck.

[RuiFaria]

Hi Edward,

I tried to use the following registers:

/*** CRGFLG - CRG Flags Register; 0x00000037 ***/

typedef union {

  byte Byte;

  struct {

    byte SCM         :1;                                       /* Self-clock mode Status */

    byte SCMIF       :1;                                       /* Self-clock mode Interrupt Flag */

    byte TRACK       :1;                                       /* Track Status */

    byte LOCK        :1;                                       /* Lock Status */

    byte LOCKIF      :1;                                       /* PLL Lock Interrupt Flag */

    byte LVRF        :1;                                       /* Low Voltage Reset Flag */

    byte PORF        :1;                                       /* Power on Reset Flag */

    byte RTIF        :1;                                       /* Real Time Interrupt Flag */

  } Bits;

} CRGFLGSTR;

/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/

typedef union {

  byte Byte;

  struct {

    byte             :1;

    byte SCMIE       :1;                                       /* Self-clock mode Interrupt Enable */

    byte             :1;

    byte             :1;

    byte LOCKIE      :1;                                       /* Lock Interrupt Enable */

    byte             :1;

    byte ILAF        :1;                                       /* Illegal Address Reset Flag */

    byte RTIE        :1;                                       /* Real Time Interrupt Enable */

  } Bits;

} CRGINTSTR

I read them on Boot of CPU but the values are always the same. :S

The bits are active:

- Track Status

- Lock Status

- PLL Lock Interrupt Flag

- Low Voltage Reset Flag

- Power on Reset Flag

- Illegal Address Reset Flag

Not always the datasheets are correct or easy to read, maybe you know that. Especially when we had short time to develop and fix things.

Best Regards,

Rui Faria

[kef2]

• I read them on Boot of CPU but the values are always the same. :S

No wonder here. Keep reading and you'll find that you need to clear flags sometimes...  (Since you don't like manuals, I guess you may have problems clearing flags properly.? It may be also that you wired something silly to /RESET pin, making CPU unable to distinguish internal vs external resets).

• Not always the datasheets are correct or easy to read, maybe you know that. Especially when we had short time to develop and fix things.

That's engineering.

[RuiFaria]

thanks for your attention