About PIT2 interrupt.

[赵子成]

Hi All,

Recently I encounter a stranger issue:

In my program I use PIT0 as  1 Millisecond timers, the program is  OK when I use P&E USB BDM Multilink to download the program(No bootloader).

But when I use bootloader, download the program via CAN com, the program seems to fail to run. The pit0 can work(the pit0 interrupt is Invalid), and if I add pit2 interrupt vector address declare in prm file and define pit2 interrupt function(Even the function content is blank) in C file, it is OK even I use bootloader mode to download the program via CAN, the program run OK, or the pit0 works OK.

I don't know why it is pit2 interrupt that  concerns whether pit0 work or not when I use bootloader download the program.

I declare the pit2 interrupt vector in prm file like this:

VECTOR ADDRESS 0x7F76 ISR_PIT2

And the pit2 interrupt function is like this:

interrupt void ISR_PIT2(void) /* vector 68 */
{
PITTF = PITTF_PTF2_MASK; 
}

And the PIT init is this:

void PIT_Init(void)
{
PITCFLMT |= 0x81; //enables the PIT module, loads the 8-bit micro timer load register into the 8-bit micro timer 0 down-counter
PITMUX |= 0x00; //The all 16-bit timer counts with micro time base 0
//pit0 period=(N+1)*(M+1)/BusClk=(59+1)*(799+1)/(48M)=1ms
PITMTLD0 = 59U; //define the timer value
PITLD0 = 799U; //define the timer value
PITINTE_PINTE0 = 1; //enable pit0 interrupt
PITFLT |= 0x01; //load the value
PITCE |= 0x01; //make the pit0 start to work
} 

[kef2]

I guess you are using banked memory model, and if so, then you need to put every ISR to nonpaged memory

#pragma CODE_SEG __NEAR_SEG NON_BANKED

interrupt void ISR_PIT2(void) /* vector 68 */
{
PITTF = PITTF_PTF2_MASK; 
}

#pragma CODE_SEG DEFAULT

• But the 《Project.prm 》show:
• PAGE_F8       = READ_ONLY   DATA_FAR IBCC_FAR  0xF88000 TO 0xF8BFFF; 

•       PAGE_F9       = READ_ONLY   DATA_FAR IBCC_FAR  0xF98000 TO 0xF9BFFF; 
•       PAGE_FA       = READ_ONLY   DATA_FAR IBCC_FAR  0xFA8000 TO 0xFABFFF; 
•       PAGE_FB       = READ_ONLY   DATA_FAR IBCC_FAR  0xFB8000 TO 0xFBBFFF; 
•       PAGE_FC       = READ_ONLY   DATA_FAR IBCC_FAR  0xFC8000 TO 0xFCBFFF;

• You can see the address is different, one is 0x7XXXXX, and one is 0xFXXXXX.

0x7XXXXX is global address, while 0xFXxxxx in PRM is banked address.

Banked address PPAGE * 0x10000 + offset to PPAGE window. For example PPAGE 0xFD, offset 0x9ABC, banked address 0xFD9ABC. And global address is PPAGE * 0x4000 + (offset % 0x4000) + 0x400000. The same banked address translates to global 0xFD * 0x4000 + 0x1ABC + 0x400000 = 7F5ABC. This applies only to flash. RAM and EEPROM address translation is different.

Edward

[danielmartynek]

Hi,

It seems like there is a problem in the bootloader.

But it's difficult to say without seeing the code.

Regards,

Daniel

[赵子成]

Hi Daniel and all other experts,

The PIT2 interrupt vector address is 0x7F76, some part of my prm file is (About interrupr vectors):

VECTOR ADDRESS 0x7F76 ISR_PIT2
VECTOR ADDRESS 0x7F78 ISR_PIT1
VECTOR ADDRESS 0x7F7A ISR_PIT0
VECTOR ADDRESS 0x7FD2 ISR_ATD0
VECTOR ADDRESS 0x7FE0 ISR_IC7
VECTOR ADDRESS 0x7FE6 ISR_IC4
VECTOR ADDRESS 0x7FA2 ISR_CAN2_Recv
VECTOR ADDRESS 0x7FA0 ISR_CAN2_Send
VECTOR ADDRESS 0x7FAA ISR_CAN1_Recv
VECTOR ADDRESS 0x7FA8 ISR_CAN1_Send
VECTOR ADDRESS 0x7FB4 ISR_CAN0_Err
VECTOR ADDRESS 0x7FB2 ISR_CAN0_Recv
VECTOR ADDRESS 0x7FB0 ISR_CAN0_Send 

Here is my some part of the download s19 file (About interrupr vectors):

S1097F7664436439642F2A
S1077FA061165F17EC
S1077FA8606A5E6D3C
S1097FB05FC15DC45D7CAD
S1057FD261C088
S1057FE06277C2
S1057FE66353DF
S105FFFE4000BD

The problem is that if I delete PIT2 interrupt address declare (Whose ISR function can be blank), Here is my some part of the download s19 file (About interrupr vectors):

S1077F786439642FD1
S1077FA061165F17EC
S1077FA8606A5E6D3C
S1097FB05FC15DC45D7CAD
S1057FD261C088
S1057FE06277C2
S1057FE66353DF
S105FFFE4000BD

I don't know why this s19 file can't work when I download to the S12 MCU.

Also I have another question:

I found the P-flash address is different between 《MC9S12XEP100MAG 》datsheet  and  《Project.prm 》, the 《MC9S12XEP100MAG 》 datsheet  say:

But the 《Project.prm 》show:

PAGE_F8       = READ_ONLY   DATA_FAR IBCC_FAR  0xF88000 TO 0xF8BFFF; 

      PAGE_F9       = READ_ONLY   DATA_FAR IBCC_FAR  0xF98000 TO 0xF9BFFF; 

      PAGE_FA       = READ_ONLY   DATA_FAR IBCC_FAR  0xFA8000 TO 0xFABFFF; 

      PAGE_FB       = READ_ONLY   DATA_FAR IBCC_FAR  0xFB8000 TO 0xFBBFFF; 

      PAGE_FC       = READ_ONLY   DATA_FAR IBCC_FAR  0xFC8000 TO 0xFCBFFF;

You can see the address is different, one is 0x7XXXXX, and one is 0xFXXXXX.

[danielmartynek]

Hi,

Regarding the last question, please see the attached memory map.

There a difference between a global address and a paged address.

Regarding PIT2, are you sure it is disabled?

Could you try using

PITINTE = 0x01;       //enable pit0 interrupt

instead of

PITINTE_PINTE0 = 1; //enable pit0 interrupt

Regards,

Daniel 

[赵子成]

Hi Daniel,

The different between PITINTE = 0x01 and PITINTE_PINTE0 = 1 remind me something.

PITINTE_PINTE0 = 1 means enabling the PIT0 interrupt but others bits remain the origenal settings. If the bit stands for PIT2 is "1", that means I also enable PIT2 interrupt.So I think maybe the PIT2 enable interrupt bit is set to "1" before APP, the only posibillity is Bootloader. I refer to the Bootloader. Oh, that is the bootloader who enable the PIT2 interrupt.

So I can explain why the APP is OK without bootloader, but not OK with bootloader.

No bootloader,  PITINTE = 0x01 is equal to PITINTE_PINTE0 = 1

With bootloader, PITINTE_PINTE0 = 1 in fact is PITINTE = 0x05(with pit2 enable in bootloader)

So I solve this problem.

Thanks Daniel.

Thanks you very much.