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e5500

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hv
Contributor II

In the e5500 core reference manual, rev. 4:

in Section 5.4.4  L1 Cache Error Detection and Correction:

L1 cache error detection occurs whenever:

   A load instruction hits in the L1 data cache

   An instruction fetch hits in the L1 instruction cache

   A line is cast out of the L1 data cache

why would "An instruction fetch hits in the L1 instruction cache" result in error?

Thanks!

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ufedor
NXP TechSupport
NXP TechSupport

If an instruction cache data or tag parity error is detected it indicates possible corrupted instruction/tag in the cache.

Parity bits can not be used to correct/recover the instruction/tag, so further instruction execution from the cache should be prevented.

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