could not use qDMA feature on LS1043A board

[ken_liu]

When I try to register and start qDMA function on LS1043A

It blocked in the first step.

following the manual reference, we should Disable the command queue.

but if set the register DMR[DQD]=1, BaCQbMR[EN]=0,  the two register could not be write succesful

(the memory map is OK)

I try write manage and block register, most of them also could not be wrote successful.

then I use TRACE32 debugged on u-boot mode, and try to modified the memory value directly

but it still doesn't work.

so it there any pre-condition for the qDMA functional on LS1043A? 

how can we use it normally

P.S:  I check the CSU\ device configuration, it is OK.  and I have switch the secure state to EL3, but it does not work.

[yipingwang]

Hello Ken Liu,

Please refer to the following procedure for qDMA engine initialization:

Try to halt the qDMA engine first.

Clear the command queue interrupt detect register for all queues.

Initialize Command Queue registers to point to the first command descriptor in memory.

Initialize the queue mode.

Initialize status queue registers to point to the first command descriptor in memory.

Initialize status queue interrupt.

Initialize the status queue mode.

Initialize controller interrupt register.

Thanks,

Yiping

[yipingwang]

There are some updates in LS1043ARM Rev5 regarding endianness of qDMA registers and descriptors.

For LS1043A,  qDMA registers are in big-endian format and its descriptors are in little-endian format. Please confirm you have used accordingly.

I have attached U-boot commands that I had used to transfer data from DDR (0xa000_0000) to PCIe EP (0x48_0000_0000) on LS1046ARDB (Same can be applied for LS1043A as well with different addresses) using command queue. Hope this will help you to understand it better.

Please check it and let me know about it.

[gregg_allen]

Hello @yipingwang. We are using the LS1043ARDB and would very much like to perform a DDR-to-DDR DMA using the qDMA engine in U-boot:

"I have attached U-boot commands that I had used to transfer data from DDR (0xa000_0000) to PCIe EP (0x48_0000_0000) on LS1046ARDB (Same can be applied for LS1043A as well with different addresses) using command queue. Hope this will help you to understand it better."
I could not find the attachment with the commands in this thread. Can you re-post or e-mail them directly to me:

gregg.allen@seakr.com

[benedikt_schroe]

Hello Yiping Wang,

can you please confirm the following:

* At first, the entire register value has to be read in big endian

* When decoding a part of the register, e.g. a bit field that spans accross multiple bits, those value has to be interpreted in little endian again?

Thanks for your help!

Best regards,

Benedikt

[yipingwang]

Hello Benedikt,

Let me explain to you with an example:

When you access qDMA register (Big-endian format) on U-Boot:

1) Assume read value: 12 34 56 78

        U-Boot command: md <qdma_register_addr>

2) Do byte swapping for decoding register. Field values directly compared with description given in RM.

        Byte Swapped value: 78 56 34 12

3) To modify the register, do it with swapped value:

    Modifying 78 as FF

        Modified value: FF 56 34 12

4) Writing to register, byte swapped again:

        Written value: 12 34 56 FF

        U-Boot command: mw.l <qdma_register_addr> 123456FF

Another example to set B0CQ0MR[EN], use below command:

mw.l 83A0800 00000080

While decoding the register, you will byte-swapped: 80 00 00 00 You can see in the RM, MSB is for EN.

Let me know if you have any confusion to understand it.

Thanks,

Yiping

[benedikt_schroe]

Hello Yiping,

thanks a lot for the detailed example, this is very helpful!

Best regards,

Benedikt

[ken_liu]

Hi Yiping Wang

Thanks a lot for your reply.  I still blocked on the first steps. following the first steps your suggestion: "Try to halt the qDMA engine first", when I use TRACE32 tool attached LS1043A on u-boot mode, try to change the qDMA register directly. (DMR[DQD], BaCQbMR[EN]), but the register could not be access.(could not be changed)

May be I miss or make some mistake. so I have two questions

Q1: for the step one:  "Try to halt the qDMA engine first",  I try to change the DMR[DQD] and BaCQbMR[EN] register value, is it right?

Q2: following the QorIQ LS1043A Reference Manual, Rev. 5, the Privileged registers may should be access under hypervisor mode. so I switch the exception level to EL3.  but it still does not work.

so pls give us a suggestion way to access the Privileged registers

thank you very much

[ken_liu]

the TRACE32 tool Directly operate the register:

[yipingwang]

Q1: for the step one: "Try to halt the qDMA engine first", I try to change the DMR[DQD] and BaCQbMR[EN] register value, is it right?

[NXP] Yes, it is right.

Q2: following the QorIQ LS1043A Reference Manual, Rev. 5, the Privileged registers may should be access under hypervisor mode. so I switch the exception level to EL3. but it still does not work.

so pls give us a suggestion way to access the Privileged registers [NXP] The Central Security Unit (CSU) sets access privilege levels for peripherals. Please check the config security level of qDMA registers at 0x151_0040. Unlock it using L1 bit and enable all SL0:7 for qDMA registers. For more details, refer CSU Memory Map/Register Definition of LS1043ARM.

Please share the following details:

3) Have you try it on LS1043ARDB and able to replicate the issue?

4) Please provide the steps which you have followed and log too.

[ken_liu]

Hi  Yiping

Thank you so much for your reply.

I have try to set the CSU register before, but it still does not work.

pls shown my steps as following

I use TRACE32 tool attach LS1043A board in u-boot mode, [u-boot version: U-Boot 2017.07-g503eff0 ]

then :

1. set CSU_CSL register and try to halt qDMA engine, but DMR[DQD] and BaCQbMR[EN] could not be set

2. I also try enable all the CSU_SA register as below, but qDMA register still can not be write

    

3.  I short the J13 and make TA_PROG_SFP power on. follow ARMv8 A53 framework. I enable all the register of the SCTLR_EL and HCR_EL2 or SCTLR_EL3 section to switch the EL2(hyp) or EL3 security level. but it still does not work

4.  the DMA1 register in DCFG_DEVDISR1 is also set to enabled.(follow the device control on manual ref)

by the way , on the default setting . only  DMR[DQOS] and DMR[TCD] and a few interrupt register can be changed.

but other important register still can not be write.

I access register bit directly on TRACE32 tool. so the address and little/big-endian format should not effect the result

pls help me review the problem.  

thank you very much

[benedikt_schroe]

Hello Ken Liu,

unfortunately, the endianness in the peripheral file for LS1043A is set to 'little' for qDMA, but it has to be set to 'big'.

We are working on a fix for this.

Please file in a request for a fixed per file at support@lauterbach.com, so that we can open a support thread for you.

You can also refer to me as a contact person.

Thanks a lot!

Best regards,

Benedikt

[benedikt_schroe]

Hello Ken Liu,

having checked your issue, we think you are probably using an older version of the per file.

Please request an update from support@lauterbach.com .

Best regards,

Benedikt