T1042 NOR FLASH Latch

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T1042 NOR FLASH Latch

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yusufalti4444
Contributor I

Hello nxp experts,

In attached image, which shows 'Figure 24-9. Connection of x16 NOR for ADM MODE 0'. We want to cover Latch with an FPGA. FPGA will do same things as exactly like if there is no FPGA. We want to use FPGA because of some voltage problems. Pins will be connected as they used to be.

Our question is;

Latch requires 1 more cycle to perform his complete task. FPGA also requires one more cycle. When we add FPGA to system, Total required cycle to write NOR flash is going to be increased from 2 to 3. (1 cycle FPGA, 1 cycle latch, 1 cycle is default) (3 cycle for latch muxing inside FPGA, 2 cyle without latch mux, only fpga).

Can this system (FPGA added) works without any problem ? If it is, what procedure should we follow to change 'IFC flash timing registers' ?

I also wonder that how this 'IP Clock' is generated inside IFC ?

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ufedor
NXP TechSupport
NXP TechSupport

You wrote:

requires one more cycle

One more cycle of which frequency?

I also wonder that how this 'IP Clock' is generated inside IFC ?

The ip clock is not generated inside the IFC.

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yusufalti4444
Contributor I

Hello,

>One more cycle of which frequency?

100MHZ

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ufedor
NXP TechSupport
NXP TechSupport

Please consider that NOR Flash is a slow device, so implementing address latch on FPGA is a viable solution.

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