T1040 flush cache

[hv]

for the T1040RDB, if I want to flush cache, do I need to flush L1 and L2 backside cache separately? 

[LPP]

dcbf instruction flushes both L1 and L2 caches.

Direct cache fluching via L1 control registers is not available for e5500.

L2 cache flush can be performed using L2CSR0[L2FL].

Have a great day,
Pavel

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[hv]

Thanks for the reply!

Would dcbst accomplish the same thing as dcbf (i.e. flushing both L1 and L2 caches)?

<http://jiveon.jivesoftware.com/mpss/c/0gA/PDcDAA/t.1rg/QZT1ok_gQ7aEHpa_HClz1Q/h0/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bQ-3D>

T1040 flush cache

reply from LPP<http://jiveon.jivesoftware.com/mpss/c/0gA/PDcDAA/t.1rg/QZT1ok_gQ7aEHpa_HClz1Q/h1/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bTbcRm-2BguqOsFIlHGSwYOeV9q6IjDGpgfEN8CsLwdyYmlwYq5OM-2B1upXUGdY5w02sc-3D> in QorIQ Processors - View the full discussion<http://jiveon.jivesoftware.com/mpss/c/0gA/PDcDAA/t.1rg/QZT1ok_gQ7aEHpa_HClz1Q/h2/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bQFQji9Ev8KZJlkte9fZPI0298fgBKpIJCrctratWHxAK-2Bvf-2B7EPe6VTofdeh5HUaM-3D>

[scottwood]

Architecturally, dcbst will cause the cache contents to be written out, if modified, but will not guarantee that the cache block is completely removed from the cache -- though on e5500, dcbst is the same as dcbf.

It should also be noted that dcbf/dcbst only flush the specified block from the data cache, which you didn't specify.  icbi is used to invalidate a block in the instruction cache.

[hv]

Sorry that I wasn’t clear.

I’m working on 3 different platforms: P2041, T1040 and T2080. I need to flush caches on all 3. I think I can use dcbf to cycle through and flush all the data cache. I just want to make sure that the dcbf/dcbst will flush both L1 & L2 data caches. The T1040 has L2 backside cache so I didn’t know if I have to do something differently for that. Would dcbf take care of flushing the data cache for the platform cache too?

Thanks!

[scottwood]

See https://community.freescale.com/message/578951?et=watches.email.thread#578951

(why did you start two threads?)

What specifically are you trying to accomplish?  Generally dcbf is used to flush a range of addresses, not the entire cache.  If you need the entire thing flushed, why?

[hv]

I started 2 threads because I thought since the other thread was marked as “answered” that I would need to create a new thread for another question.

Yes, I know that dcbf is used to flush a range of addresses, not the entire cache. But I thought I can use it to cycle through the range and flush the entire cache. But that’s when I need to make sure that dcbf would flush all caches.

Why do I need the entire thing flushed, because we’re doing benchmark study and the results we got showed to show that the T1040 is much slower (2 or 3 times slower) than the T2080. We think it’s due to the cache size since the test code we used for the benchmark is a very big piece of code that we think that’s why it’s showing that much of a difference between the 2 processors. To prove/disprove that theory, we think that flushing cache cache on the processors before running the test code would give us more insights.

T1040 flush cache

reply from Scott Wood<http://jiveon.jivesoftware.com/mpss/c/mQA/PDcDAA/t.1rg/NLobBRrVTBK9jVFm3AV_9A/h1/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bSdP5biIGukMJCDP2RcupmsPmgsYXI6jS0m1mNZQcP1yOyvoqXPJhZYDmN8R-2F7Wf2U-3D> in QorIQ Processors - View the full discussion<http://jiveon.jivesoftware.com/mpss/c/mQA/PDcDAA/t.1rg/NLobBRrVTBK9jVFm3AV_9A/h2/eqhG5v9o4WV1pCmWaB03cUjBPgRj-2F3GoJUaXSZ409bRBHj65nfOA-2FAOLmwOMEWzpe6Pz2Ey8p1mc1DKq76Htux8Ms39qJBOzCmPG5-2FWSTwA-3D>