T1040 IFC NOR ADDR Timing

[nsutch]

I have read and the Datasheet and Reference Manual for the T1040 IFC interface for NOR Flash - my design uses simple/asynchronous NOR PC28F00BM29EWHA with an external latch. I've created a timing diagram for a burst read cycle much like in Figure 24-39 of the RM but what I can't work out is what governs the address valid periods for ADDR0, ADDR1, ADDR2 etc (Names are in reference to figure 24-39) ??

I feel like I need this to make sure the address is valid for long enough at the flash device as well as ensuring the sample point is in the middle of the valid period of the data coming back to the T1040. I can't see in the documents a register setting or paramter for this - or am I misunderstanding somthing?

Thanks in advance,

Nick

[Bulat]

Both timing parameters are set in the IFC_FTIM1_CSn_NOR register. See chapter 24.3.15 of the Manual.

Regards,

Bulat

[nsutch]

Hi Bulat,

Thanks for taking the time to respond. Please could you be more explicit about which timing parameter name(s) you are refering to. As I mentioned, I have looked at the RM, including the FTI register and used the parameters in accordance with Figure 24-39. 

TACO is stated as the relationship between CS transitioning low and OE transitioning low

TRAD & TSEQRAD is stated as the point at which the data will be ready to sample at the processor.

What I am after is the timing parameters that govern when the ADDR bus is valid.

Thanks,

Nick

[yipingwang]

Hello Nick Sutch,

Please refer to document IFC Controller Configuration on QorIQ Custom Boards  for IFC controller configuration when bringing up new target boards.

Have a great day,
TIC

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[Bulat]

In terms of ip_clk cycles the address timing is as following:

ADDR0 = TEADC + TEAHC + TACSE + TACO + TRAD +3;

ADDR1 = TSEQRAD + 5;

ADDR2 = TSEQRAD + 5;

...

etc

Regards,

Bulat

[nsutch]

Thank you Bulat, that is the information I was after. Could you tell me where this was derived from?

Thanls,

Nick