T1024 IFC NOR Flash Interface timing question

[matthewcharman]

The question I have is about the T1024 NOR Flash interface timing. We are interfacing to the Micron NOR flash (JS28F00AM29EWHA) which is the same as on the Reference Board Design for this processor.

• The concern we have is with regards to Hold Time for a Read Cycle (Figure 23-38 from the T1024 Reference Manual).
• Per the datasheet, the T1024 requires 5ns hold time (based on a 200MHz ip_clk)
• The NOR flash (JS28F00AM29EWHA) doesn’t provide any hold time after OE, CE or ADDR are negated

In summary the T1024 datasheet doesn’t clearly show the relationship between when the data is sampled by the T1024, and when OE, CE or ADDR are negated by the T1024 – this information is required to show that the hold time requirement is met.

Are you able to clarify?

[Pavel]

Yes, the green timing is correct. See the T1024 Datasheet. See the Table 85 and Figure 36 of the T1024 Datasheet Rev 0.

Have a great day,
Pavel Chubakov

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[Pavel]

Yes, you are right. The TRAD represents the data sampling time of read data.

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

And what about the other markup in light green? I would also like your confirmation that this is correct as well. Marked up Figure 23-38 attached/below again.

Regards,

Matthew

[Pavel]

You are right. The Datasheet is not certainly clear.

The tIBIXKH2 shows hold time concerning to internal clock.

The Sample signal on the Figure 23-38 is signal concerning to this internal clock.

The filling edge of the Sample should be before negation of OE. It can be produced setting correct TRAD value.

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

Thanks for your feedback. Really is appreciated, but is it possible for you to confirm my marked up Figure 23-38 (attached) is correct?

Regards,

Matthew

[Pavel]

The Figure 36 of the T1024 Datasheet shows that after [(TRAD +1)* tIP_CLK + tIBIXKH2] of the falling edge of the OE_B signal. The tIBIXKH2 minimal value is 1 x tIP_CLK. See the Table 85 of the T1024 Datasheet. As result  minimal time for negation of CS_B, ADDR and OE_B signals occurs  after [(TRAD +2)* tIP_CLK] of the falling edge of the OE_B signal.

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

This would be great if it’s true – are you certain what you stated is correct? That the minimal time for negation of CS_B, ADDR and OE_B signals is after the falling edge of the OE_B signal. Please confirm again as this is particularly important for our timing analysis & design.

Note the reason I’m asking you to check again is because the datasheet certainly isn’t clear. Figure 36 & Table 85 say they are for “Input timing specifications”. So my interpretation is that tIBIXKH2 is telling me the hold time requirement on the T1024 data inputs and not how much time CS_B, ADDR and OE_B signals will be held active (low). In addition Figure 36 doesn’t even show CS_B or ADDR.

I’ve marked up Figure 23-38 again to show what you are saying visually (attached) – please let me know if you think I’ve made a mistake on the markup.

Regards,

Matthew

[Pavel]

The T1024 IFC samples data after TRAD time of the falling edge of the OE_B.

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

So you have confirmed that my marked up diagram which shows the T1024 IFC samples data after TRAD time of the falling edge of the OE_B signal is correct.

Now what about the negation of CS_B, ADDR and OE_B? Per my diagram I have shown that this occurs after TRAD time plus 1 x tIP_CLK of the falling edge of the OE_B signal. Is that correct?

Regards,

Matthew

[Pavel]

The T1024 IFC using internal clock for data sampling. The T1024 IFC does not use rising edge of the OE for data sampling.

Look at Figure 36 of the T1024 Datasheet:

https://www.nxp.com/webapp/Download?colCode=T1024&location=null&fpsp=1&WT_TYPE=Data%20Sheets&WT_VEND...

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

Thanks for your reply.

It is understood that the T1024 IFC uses the internal clock for data sampling and that the T1024 IFC doesn’t use the rising edge of the OE for data sampling, however the same questions from my previous post still remain. I’ve marked up Figure 23-38 from the reference manual – maybe you can tell me if my markup is correct?

Regards,

Matthew

[Pavel]

The T1024 IFC samples data using internal clock. The tIBIXKH2 shows hold time for this internal clock.

The Micron NOR flash (JS28F00AM29EWHA) shows that data valid as maximum 25ns after OE assertion. Find the tGLQV parameter of the JS28F00AM29 Datasheet.

The T1024 IFC provides TRAD parameter.  If TRAD value is more then 25ns, the T1024 correctly  read data from the JS28F00AM29 Flash.

Have a great day,
Pavel Chubakov

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[matthewcharman]

Hi Pavel,

Thanks for your reply.

I’m not sure if you understood the question properly. What I am concerned with is that Hold time requirement for the T1024 processor is met. The tIBIXKH2 parameter is the hold time requirement of the processor. In my case its 5ns based on a 200MHz ip_clk. i.e. my understating is that data must be held on the data bus (at input of T1024) for 5ns after the data is sampled by the T1024.

Per the NOR flash (JS28F00AM29EWHA) datasheet, the NOR flash doesn’t provide any hold time after OE, CE or ADDR are negated – see parameter tOH in the NOR flash datasheet (it’s 0ns min).

So my question is – how can I ensure the T1024 hold time requirement (tIBIXKH2) is satisfied?

Regards,

Matthew