I have a new design with a blank QSPI, so there is no RCW. I cannot get the Bare Board bring-up to run because the DDR DRAM is failing. I tried to read the SPD with a QorIQ Configuration Project. However, that does not work either. I put a scope on the I2C lines going to the DIMM and they never toggle. When I try to Read the SPD, the TX/RX LEDs on the Code Warrior flash, so I know that hardware got the commands.
Code Warrior is
Version: 11.5.2
Build Id: 210130
The error messages in the Wizard are shown below. It appears from the python code that those messages reference, that it is trying to do an additional reset since it thinks there is a valid RCW loaded. However, there is not! I cannot find a setting in the project to tell it to use a safe RCW.
In the Bare Board project, if I diagnose the debugger connection, then it fails at DDR Init and fatally fails at the DDR Write to 0x80000000
Questions:
1. What am I missing or doing wrong to read the SPD?
2. Is there a way to by-pass the DRAM test in the Bare Board debugger to at least be able to program the QSPI so the RCW is present?
Thanks.
**********************************************************************************************
RCWSR1:
[0L]
Traceback (most recent call last):
File "C:\Freescale\CW4NET_v2020.06\Common\QCVS\Optimization\resources\QorIQ\ARMv8/ddr/read_spd.py", line 205, in <module>
read_spd()
File "C:\Freescale\CW4NET_v2020.06\Common\QCVS\Optimization\resources\QorIQ\ARMv8/ddr/read_spd.py", line 162, in read_spd
sys_init.init(params, session, init_ddr=False)
File "C:\Freescale\CW4NET_v2020.06\Common\QCVS\Optimization\resources\QorIQ\ARMv8\ddr\sys_init.py", line 150, in init
reset_out = utils.gdb_execute("cw_reset %d" % reset_delay)
File "C:\Freescale\CW4NET_v2020.06\Common\QCVS\Optimization\resources\QorIQ\ARMv8\common\utils.py", line 215, in gdb_execute
raise gdb.GdbError("ERROR: " + str(ex))
gdb.GdbError: ERROR: Target reset failed.
//
Additional error details:
[CCS: timeout during target operation]