QorIQ PCIe Link Control 2 Register questions

cmc_dave · ‎08-26-2019

I need to tune the PCIe lanes driven by a P3041(Gen 1 x 4)

I see in the QorIQ P3041 Reference manual on page 1203 the bit definitions for the Link_Control_2_Register.

Can you point me to a document that would explain what these bit settings do in more detail please?

What is Compliance de-emphasis vs Selectable de-emphasis? What do the Transmit margin bits do?

Thanks

for you help

Dave R

cmc_dave · ‎08-27-2019

Thank you for the detailed response.

Dave R

yipingwang · ‎08-27-2019

Hello DAVID ROBERTS,

Please refer to the following document.

PCI Express® Base Specification Revision 4.0 Version 1.0

Compliance Preset/De-emphasis –
For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in Section 4.2.3.2. Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.
For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
Defined Encodings are:
0001b -3.5 dB
0000b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.
For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.
The default value of this field is 0000b.
This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.

Selectable De-emphasis – When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. See Section 4.2.6 for detailed usage information.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.
This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.

Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 for details of how the Transmitter voltage level is determined in various states).
Encodings:
000b Normal operating range
001b-111b As defined in Section 8.3.4 not all encodings are required to be implemented.
For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.
Default value of this field is 000b.
Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 000b.
This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.

Thanks,

Yiping