In our custom board, we configured Serdes3 for PCIe as SRDS_PRTCL_S3 = 1 and connected to PCIe switch as 8x. The configuration is done in RCW. After power T4240 is not coming out of reset as reset_reqB signal is low. So we configured SRDS_PRTCL_S3 = 3 in RCW, T4240 boots properly and detects the PCIe controller. But though PCie configured in Root complex mode, PCI scan in U-boot not able to detect the PCIe switch. Both the cases PLL2 is powered down as we don't have PLL2 clock in our configuration. Is PLL2 clock required for SRDS_PRTCL_S3 = 1.
1. Why reset_reqB signal is going low when PCIe configured as 8x using SRDS_PRTCL_S3 = 1 in RCW.
2. PCI scan is not able detect the swtich though its boots properly when SRDS_PRTCL_S3 = 3.
rgds,
sk
