(PCI Configuration) dbt source file

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

(PCI Configuration) dbt source file

Jump to solution
890 Views
manoloruiz
Contributor III

I am reading the next file:
http://cache.nxp.com/files/32bit/doc/app_note/AN5125.pdf?pspll=1

But I have some doubts about PCI device configuration in the device tree blob.

1     pci1: pcie@ffe09000 {

2         reg = <0 0xffe09000 0 0x1000>;

3          ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 //everything is clear for me

4                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; //everything is clear for me

5           pcie@0 {

6                   ranges = <0x2000000 0x0 0xa0000000 //phys.hi+ phys.mid +phys.low

7                                    0x2000000 0x0 0xa0000000 //I dont know what means

8                                  0x0 0x20000000                    //I dont know what means

9

10                                 0x1000000 0x0 0x0             //phys.hi+ phys.mid +phys.low

11                                 0x1000000 0x0 0x0         //I dont know what means

12                                 0x0 0x100000>;             //I dont know what means

     };

};

Could you help me with the line that are not explained in the pdf file?

Labels (1)
Tags (2)
0 Kudos
1 Solution
644 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello manolo ruiz,

ranges(child-bus-address, parent-bus-address, length)

It provides a means of defining a mapping or translation between the physical address space of the bus (the child address space) and the physical address space of the bus node’s parent (the parent address space).

The child-bus-address is a physical address within the child bus’ address space.

The parent-bus-address is a physical address within the parent bus’ address space.

In the above PCIe device tree definition, the child PCIe at offset 0x0 is from parent PCIe at 0xffe09000, the child PCIe memory space at 0x0_a0000000 maps to the parent PCIe memory space at 0x0_a0000000, the size is 0x20000000. The child PCIe I/O space address at 0x0 maps the parent PCIe I/O space address at 0x0, the size is 0x100000.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
1 Reply
645 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello manolo ruiz,

ranges(child-bus-address, parent-bus-address, length)

It provides a means of defining a mapping or translation between the physical address space of the bus (the child address space) and the physical address space of the bus node’s parent (the parent address space).

The child-bus-address is a physical address within the child bus’ address space.

The parent-bus-address is a physical address within the parent bus’ address space.

In the above PCIe device tree definition, the child PCIe at offset 0x0 is from parent PCIe at 0xffe09000, the child PCIe memory space at 0x0_a0000000 maps to the parent PCIe memory space at 0x0_a0000000, the size is 0x20000000. The child PCIe I/O space address at 0x0 maps the parent PCIe I/O space address at 0x0, the size is 0x100000.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos