P2040: PCIe testing between two processors

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P2040: PCIe testing between two processors

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gouravjain
Contributor IV

Hi All,

My board is having 2 P2040 chipset. And both are connected via PCIe lines. 
I want to perform some data transfer between processors over PCIe interface.

Have very limited knowledge about PCIe. Till now i understood that one processor has to be in Root complex mode and another one has to be end point.
My doubts are,

1) How to configure processors for RC/Endpoints. What all configurations i need to see (RCW/kernel/device driver side)

2) Is there any application code for user space??

Thanks in advance !!

Gourav

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bpe
NXP TechSupport
NXP TechSupport

PCIe host/agent mode is selected in RCW. Refer to P2040RM, Table 4-10,
description of RCW fields HOST_AGT_B1 and HOST_AGT_B2. As of Linux,
NXP QorIQ SDK builds everything for RC by default. For EP support and

configuration available in the SDK, visit the links below:

https://nxp.sdlproducts.com/LiveContent/content/en-US/QorIQ_SDK/GUID-A745CFCF-79F4-46DA-A7D3-AF7B246...

https://nxp.sdlproducts.com/LiveContent/content/en-US/QorIQ_SDK/GUID-E4D92701-4401-4905-89E5-692D647...

Note, SKMM-EP software exercising cryptography mentioned in the first

article is not valid for your processor as it requires a later version of cryptographic

accelerator, SEC. However, you can try the DMA test described in the second one.


Have a great day,
Platon

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gouravjain
Contributor IV

Hi Platon,

Thanks for addressing my query...
I Have tried to enable PCIe in RC mode already, like your way. But u-boot log indicates it's not enabled yet.

If you look into RCW values, bits 128-133, serdes_prtcl: 0x0F and bits 264-267: all 0.

So i guess RCW is fine but still u-boot log says PCIe disabled.

Here is the log,


U-Boot 2013.01 (May 15 2019 - 17:57:51)

CPU0: P2040E, Version: 2.0, (0x82180020)
Core: E500MC, Version: 3.2, (0x80230032)
Clock Configuration:
CPU0:800 MHz, CPU1:800 MHz, CPU2:800 MHz, CPU3:800 MHz,
CCB:400 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:50 MHz
FMAN1: 200 MHz
QMAN: 200 MHz
PME: 200 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Reset Configuration Word (RCW):
00000000: 4c180000 00000000 58540000 00000000 [0-127]
00000010: 3c8e90c0 f7c02000 de800000 04000000 [128-255]
00000020: 00000000 00000000 00000000 c8028300 [256-383]
00000030: 00000000 00000000 00000000 00000000 [384-511]


HNS_P0 Board: P2040, vBank: 0

I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM HMT451S6BFR8C-PB
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=6, ECC off)
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2: N/A
Corenet Platform Cache: 1024 KB enabled
Using SERDES configuration 0xf, lane settings:
SERDES: bank 3 disabled
SRIO1: disabled
SRIO2: disabled
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
GJ:PCIe3: disabled
In: serial
Out: serial
Err: serial
Net: Initializing Fman
sgmii interface @ DTSEC1
sgmii interface @ DTSEC2
sgmii interface @ DTSEC3
Fman1: Uploading microcode version 106.1.4
PHY reset timed out
FM1@DTSEC1 connected to Generic PHY at phy_addr:30
PHY reset timed out
FM1@DTSEC2 connected to Generic PHY at phy_addr:31
PHY reset timed out
FM1@DTSEC3 connected to Generic PHY at phy_addr:2
PHY reset timed out
PHY reset timed out
FM1@DTSEC1, FM1@DTSEC2 [PRIME], FM1@DTSEC3, ,
Hit any key to stop autoboot: 0

Pls let me know any more flags are required to set, if any.

Thanks...

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gouravjain
Contributor IV

Hi Platon,

Waiting for your reply...

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