P2020 power sequencing

[toddreed]

Hello,

I see in the datasheet that GVDD should be the last rail powered up.  We are using DDR3, so our GVDD is 1.5V.

I see in other posts that GVDD should be powered up last so that MCKE is held low during power on so that the DDR is not accidentally clocked.  What are the negative effects of this?  Can the DDR be put in a bad state?  Our processor is being held in reset long after all powers are established and we have a DDR_RST# line we can assert to the DDR during power on, so would these supercede the need for GVDD power sequencing?  The 1.5V rail also connects to our FPGA core, so there is a race condition if we must power GVDD last.

Thank you,

Todd

[Bulat]

You are right, GVDD sequencing requirement concerns with MCKE state during reset. This is important if your design supports deep sleep feature, when the memory stays in self-refresh/power-down mode with fresh data while the processor is powered down. In this case the data in the memory can be corrupted during processor power up due to MCKE glitch. If you are not going to use this functionality, GVDD can be powered up alone with other supplies.

Regards,

Bulat

[toddreed]

Hello Bulat,

Thank you for the information.  The datasheet states that "all supplies must be at their stable values within 50 ms".  What are the consequences of them not all being at their stable values within 50ms?  In one of our configurations the 1.05V rail will not be enabled until after an FPGA is loaded, meaning the P2020 will have 1.5V and 3.3V applied to it for a few minutes without the 1.05V.  Would this risk potential damage to the part?

Thank you,

Todd