P1022 Power sequencing

[zeevg]

Hi,

The P1022 Power sequencing is (from DS):

1. VDDC, VDD, AVDD_PLAT, AVDD_DDR, LVDD2, OVDD2, AVDD_CORE0, AVDD_CORE1, BVDD, LVDD, OVDD,
SVDD, SVDD2, XVDD, XVDD2, SDAVDD, SDAVDD2

2. GVDD

What is the recommended delay between stage 1 to stage 2?

Pls. advise

Zeev Gerber

[alexander_yakov]

There is no recommended delay between these voltages, the only maximum time is specified - all voltages must reach their values within 50 ms.

Minimum time between voltages from first line and voltage from second line - is not specified. The only requirement is - all voltages from first line must reach at least 90% from their values before voltage from second line reach 10%.

Also please note - this specific requirement is only in order to guarantee MCKE low during power-up. If there is no requirement for MCKE in your design, than specific sequencing for GVDD is not required.

Have a great day,
Alexander

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