MPC8347 CPU Local Bus Timing

[sharper]

With the DLL in bypass mode and with OR[EAD] set to 0, LALE should be asserted for one bus clock cycle only.

What is the hold time of the LALE signal from the falling edge of LCLK?

[r8070z]

Have a great day,

It is not specified as for LALE as for LAD in the DLL bypass mode. Only LAD hold time from the falling edge of LALE is specified in this mode. It is supposed that address is latched on LALE transition while LCLK is irrelevant in this case.

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