I looked into the sections below. Power-on & Hard reset performs a reset of the entire device. This is not the case with other reset sources. How is the WDOGRES handled in the SoC ?
4.7.1 Reset Operations
The platform supports several inputs to reset the platform logic and/or core(s):
• Power-on reset (PORESET_B) of entire device
• External hard reset (HRESET_B) of entire device
• Core watchdog timer expiration from each core with specific WRS encoding
• Individual core reset requests from the respective cores
• Interrupt controller reset request of a core or cores initiated by software write to PIC
PIR register
4.7.2 Reset Actions
The reset control logic determines the cause of the reset, synchronizes it if necessary, and
resets the appropriate internal hardware. Each type of reset has a different impact on the
device logic:
• Power-On Reset has the greatest impact, sampling the POR configuration pins ,
resetting the entire device, including all clocking logic PLLs and fuse-related logic.
• Hard Reset resets the entire device, with the exception of:
PLLs in some cases
fuse-related logic in all cases
• Warm Device Reset is very similar to Hard Reset but reapplies the repair information
across the chip since portions have had power removed
• Other sources of reset mentioned simply cause a reset of the state of a given core.
Registers that store fuse related information for that core are not reset.